Patents by Inventor Larry D. Larsen

Larry D. Larsen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6408382
    Abstract: An improved manifold array (ManArray) architecture addresses the problem of configurable application-specific instruction set optimization and instruction memory reduction using an instruction abbreviation process thereby further optimizing the general ManArray architecture for application to high-volume and portable battery-powered type of products. In the ManArray abbreviation process a standard 32-bit ManArray instruction is reduced to a smaller length instruction format, such as 14-bits. An application is first programmed using the full ManArray instruction set using the native 32-bit instructions. After the application program is completed and verified, an instruction-abbreviation tool analyzes the 32-bit application program and generates the abbreviated program using the abbreviated instructions. This instruction abbreviation process allows different program-reduction optimizations tailored for each application program. This process develops an optimized instruction set for the intended application.
    Type: Grant
    Filed: October 21, 1999
    Date of Patent: June 18, 2002
    Assignee: Bops, Inc.
    Inventors: Gerald G. Pechanek, Charles W. Kurak, Jr., Larry D. Larsen
  • Publication number: 20020073299
    Abstract: A hierarchical instruction set architecture (ISA) provides pluggable instruction set capability and support of array processors. The term pluggable is from the programmer's viewpoint and relates to groups of instructions that can easily be added to a processor architecture for code density and performance enhancements. One specific aspect addressed herein is the unique compacted instruction set which allows the programmer the ability to dynamically create a set of compacted instructions on a task by task basis for the primary purpose of improving control and parallel code density. These compacted instructions are parallelizable in that they are not specifically restricted to control code application but can be executed in the processing elements (PEs) in an array processor. The ManArray family of processors is designed for this dynamic compacted instruction set capability and also supports a scalable array of from one to N PEs.
    Type: Application
    Filed: September 28, 2001
    Publication date: June 13, 2002
    Inventors: Gerald G. Pechanek, Edwin F. Barry, Juan Guillermo Revilla, Larry D. Larsen
  • Patent number: 6397324
    Abstract: A very long instruction word (VLIW) processor typically requires a large number of register file ports due to the parallel execution of the sub-instructions comprising the VLIW. By splitting a general purpose register file into separate address and compute register files, the number of compute register file ports is significantly reduced. This reduction is particularly evident when multiple load and store execution units with indexed addressing modes are supported. The implication is that a faster register file and dedicated address registers are achieved in the programming model. The savings comes at the cost of providing support for data movement between the compute register file and the address register file. In addition, address arithmetic, table look-up, and store to table functions are desirable functions that cannot be obviously obtained when the address registers are separated from the compute registers.
    Type: Grant
    Filed: June 16, 2000
    Date of Patent: May 28, 2002
    Assignee: BOPS, Inc.
    Inventors: Edwin Frank Barry, Charles W. Kurak, Jr., Gerald G. Pechanek, Larry D. Larsen
  • Publication number: 20010049763
    Abstract: Hardware and software techniques for interrupt detection and response in a scalable pipelined array processor environment are described. Utilizing these techniques, a sequential program execution model with interrupts can be maintained in a highly parallel scalable pipelined array processing containing multiple processing elements and distributed memories and register files. When an interrupt occurs, interface signals are provided to all PEs to support independent interrupt operations in each PE dependent upon the local PE instruction sequence prior to the interrupt. Processing/element exception interrupts are supported and low latency interrupt processing is also provided for embedded systems where real time signal processing is required. Further, a hierarchical interrupt structure is used allowing a generalized debug approach using debut interrupts and a dynamic debut monitor mechanism.
    Type: Application
    Filed: February 23, 2001
    Publication date: December 6, 2001
    Inventors: Edwin Frank Barry, Patrick R. Marchand, Gerald G. Pechanek, Larry D. Larsen
  • Patent number: 6321322
    Abstract: A hierarchical instruction set architecture (ISA) provides pluggable instruction set capability and support of array processors. The term pluggable is from the programmer's viewpoint and relates to groups of instructions that can easily be added to a processor architecture for code density and performance enhancements. One specific aspect addressed herein is the unique compacted instruction set which allows the programmer the ability to dynamically create a set of compacted instructions on a task by task basis for the primary purpose of improving control and parallel code density. These compacted instructions are parallelizable in that they are not specifically restricted to control code application but can be executed in the processing elements (PEs) in an array processor. The ManArray family of processors is designed for this dynamic compacted instruction set capability and also supports a scalable array of from one to N PEs.
    Type: Grant
    Filed: April 5, 2000
    Date of Patent: November 20, 2001
    Assignee: BOPS, Inc.
    Inventors: Gerald G. Pechanek, Edwin F. Barry, Juan Guillermo Revilla, Larry D. Larsen
  • Patent number: 6128720
    Abstract: A multi-processor array organization is dynamically configured by the inclusion of a configuration topology field in instructions broadcast to the processors in the array. Each of the processors in the array is capable of performing a customized data selection and storage, instruction execution, and result destination selection, by uniquely interpreting a broadcast instruction by using the identity of the processor executing the instruction. In this manner, processing elements in a large multi-processing array can be dynamically reconfigured and have their operations customized for each processor using broadcast instructions.
    Type: Grant
    Filed: April 10, 1997
    Date of Patent: October 3, 2000
    Assignee: International Business Machines Corporation
    Inventors: Gerald G. Pechanek, Larry D. Larsen, Clair John Glossner, Stamatis Vassiliaadis
  • Patent number: 6101592
    Abstract: A hierarchical instruction set architecture (ISA) provides pluggable instruction set capability and support of array processors. The term pluggable is from the programmer's viewpoint and relates to groups of instructions that can easily be added to a processor architecture for code density and performance enhancements. One specific aspect addressed herein is the unique compacted instruction set which allows the programmer the ability to dynamically create a set of compacted instructions on a task by task basis for the primary purpose of improving control and parallel code density. These compacted instructions are parallelizable in that they are not specifically restricted to control code application but can be executed in the processing elements (PEs) in an array processor. The ManArray family of processors is designed for this dynamic compacted instruction set capability and also supports a scalable array of from one to N PEs.
    Type: Grant
    Filed: December 18, 1998
    Date of Patent: August 8, 2000
    Assignee: Billions of Operations Per Second, Inc.
    Inventors: Gerald G. Pechanek, Edwin F. Barry, Juan Guillermo Revilla, Larry D. Larsen
  • Patent number: 5682491
    Abstract: An array processor topology reconfiguration system and method enables processor elements in an array to dynamically reconfigure their mutual interconnection for the exchange of arithmetic results between the processors. Each processor element includes an interconnection switch which is controlled by an instruction decoder in the processor. Instructions are broadcast to all of the processors in the array. The instructions are uniquely interpreted at each respective processor in the array, depending upon the processor identity. The interpretation of the commonly broadcast instruction is uniquely performed at each processor by combining the processor identity for the executing processor, with a value in the instruction. The resulting control signals from the instruction decoder to the interconnection switch, provides for a customized linkage between the executing processor and other processors in the array.
    Type: Grant
    Filed: December 29, 1994
    Date of Patent: October 28, 1997
    Assignee: International Business Machines Corporation
    Inventors: Gerald G. Pechanek, Larry D. Larsen, Clair John Glossner, Stamatis Vassiliaadis, Daniel H. McCabe
  • Patent number: 5659785
    Abstract: A plurality of processor elements (PEs) are connected in a duster by a common instruction bus to a sequencing control unit with its associated instruction memory. Each PE has data buses connected to at least its four nearest PE neighbors, referred to as its North, South, East and West PE neighbors. Each PE also has a general purpose register file containing several operand registers. A common instruction is fetched from the instruction memory by the sequencing control unit and broadcast over the instruction bus to each PE in the cluster. The instruction includes an upcode value that controls the arithmetic or logical operation performed by an execution unit in the PE on one or more operands in the register file. A switch is included in each PE to interconnect it with a first PE neighbor as the destination to which the result from the execution unit is sent.
    Type: Grant
    Filed: February 10, 1995
    Date of Patent: August 19, 1997
    Assignee: International Business Machines Corporation
    Inventors: Gerald G. Pechanek, Larry D. Larsen, Clair John Glossner, Stamatis Vassiliaadis
  • Patent number: 5659722
    Abstract: A data processing system includes a number of processing elements wherein each of the processing elements generates one or more condition signals, one or more memory elements associated with the processing elements for storing instructions and data associated with the processing elements, at least one register for storing a predicate associated with each of the processing elements and logic for comparing condition signals from each of the processing elements with a corresponding predicate to generate one or more branch test signals, and combination logic to provide a single take branch signal based on branch test signals and logic masks associated with each of the predicates.
    Type: Grant
    Filed: April 28, 1994
    Date of Patent: August 19, 1997
    Assignee: International Business Machines Corporation
    Inventors: Bartholomew Blaner, Larry D. Larsen
  • Patent number: 5649135
    Abstract: A parallel processing system and method is disclosed, which provides an improved instruction distribution mechanism for a parallel processing array. The invention broadcasts a basic instruction to each of a plurality of processor elements. Each processor element decodes the same instruction by combining it with a unique offset value stored in each respective processor element, to produce a derived instruction that is unique to the processor element. A first type of basic instruction results in the processor element performing a logical or control operation. A second type of basic instruction results in the generation of a pointer address. The pointer address has a unique address value because it results from combining the basic instruction with the unique offset value stored at the processor element. The pointer address is used to access an alternative instruction from an alternative instruction storage, for execution in the processor element.
    Type: Grant
    Filed: January 17, 1995
    Date of Patent: July 15, 1997
    Assignee: International Business Machines Corporation
    Inventors: Gerald G. Pechanek, Clair John Glossner, Larry D. Larsen, Stamatis Vassiliadis
  • Patent number: 5371872
    Abstract: The use of a high speed cache memory may be selectively controlled when a data processing task is interrupted in response to an interrupt signal, in order to prevent the interrupt from chilling the cache when insufficient performance enhancement will be realized. Disturbing the cache memory during performance of an interrupting task is prevented, thereby increasing the hit ratio of the cache when the interrupted task is resumed. Cache control information may be incorporated into a program status vector or program status word which is loaded into a program status register on occurrence of an interrupt.
    Type: Grant
    Filed: October 28, 1991
    Date of Patent: December 6, 1994
    Assignee: International Business Machines Corporation
    Inventors: Larry D. Larsen, David W. Nuechterlein, Kim E. O'Donnell, Lee S. Rogers, Thomas A. Sartorius, Kenneth D. Schultz, Harry I. Linzer
  • Patent number: 5115500
    Abstract: Architectural design of processor apparatus and its method of operation permit normally incompatible plural format process instructions for dissimilar processors to be placed intermixed in the instruction storage of a single machine but to be accurately decoded and executed properly regardless. Instructions in different formats which are normally incompatible which may have been written for different machine types are placed in predefined or segregated areas of the instruction store. Instructions are fetched and decoded by the processor for execution in a manner which uses portions of both the fetched-from address in the instruction store and the instruction itself. Decoding is thus determined in part by where in the instruction store the instruction resided when fetched, and the specific instruction itself. This approach is compatible with both ordinary processor architecture and with pipelined processor architectures.
    Type: Grant
    Filed: January 11, 1988
    Date of Patent: May 19, 1992
    Assignee: International Business Machines Corporation
    Inventor: Larry D. Larsen
  • Patent number: 5081574
    Abstract: The architecture and instructions of the processor utilized in the present invention permit efficient accomplishment of signal processing tasks. A three phase pipelined operation for instructions exists consisting of fetch, decode, and execute operations. To provide additional flexibility and reduce branch latency, all of the instructions executed except for branch instructions are executed on phase three. Branch instructions are caused to execute at the end of phase two. The branching conditions may be on the basis of "hot bits" existing within the processor during the second cycle and resulting from the execution of the instruction just preceding the branch instruction. Conditional branches are performed based upon conditions not previously latched into registers that result from the execution of such instructions. These conditions are generated at the same time that the branch will be executed.
    Type: Grant
    Filed: February 26, 1990
    Date of Patent: January 14, 1992
    Assignee: International Business Machines Corporation
    Inventors: Larry D. Larsen, Daniel J. Esteban
  • Patent number: 4794517
    Abstract: This processor is a single chip implementation of an architecture that is designed to expeditiously handle certain tasks commonly associated with signal processing. Sequential multiply and accumulate operations, in particular, can be accomplished quite efficiently. The processor is pipelined in two areas. Instructions are passed through a three phase pipeline and consist of fetch, decode and execute, while the multiplier utilizes a two phase pipeline. The data flow is parallel and of 16-bit width throughout. The instruction store is maintained separately from the data store and provisions are included for having the processor enabled to read and write its own instruction store. Some parallel or compound instructions are implemented to permit transfer actions such as storage or I/O to or from instruction registers to occur concurrently with a compute action in different segments of the data flow. The arithmetic capabilities of the processor include both the separate multiplier and a full arithmetic logic unit.
    Type: Grant
    Filed: April 15, 1985
    Date of Patent: December 27, 1988
    Assignee: International Business Machines Corporation
    Inventors: Gardner D. Jones, Larry D. Larsen, Daniel J. Esteban
  • Patent number: 4691794
    Abstract: A strain gauge assembly of the type having an elongate flexible member (12) with attached strain gauges (36, 38) has forces applied thereto at points (48, 50) spaced from its central neutral plane (52) by means including members mounted to a foot (10) and force receiving (14) members for non-sliding lateral movement relative thereto. In another embodiment strain gauges are attached to a flexible diaphragm (68) which is in communication with a fluid contained within a flexible sealed container (78) that is restrained against lateral movement by a hollow restraint member (62) therearound but which has a portion (80) protruding from a lower open end (66) thereof to receive a load to pressurize the fluid for flexing the diaphragm (68).
    Type: Grant
    Filed: September 4, 1984
    Date of Patent: September 8, 1987
    Assignee: Fyrnetics, Inc.
    Inventors: Larry D. Larsen, Richard C. S. Yung, Wing K. Leung, Joseph E. Hogel
  • Patent number: 4663675
    Abstract: An improved method and apparatus of digital speech storage and retrieval is described utilizing silence gaps for insertion of control signal information. This prevents interference with incoming control signals by feedback of signals through the hybrid circuit that occurs during playback of the stored speech. A diverter switch is controlled during the playback mode to allow incoming control signals to be decoded only when gaps of sufficient length are detected in the played back program.
    Type: Grant
    Filed: May 4, 1984
    Date of Patent: May 5, 1987
    Assignee: International Business Machines Corporation
    Inventors: Gardner D. Jones, Jr., Larry D. Larsen
  • Patent number: 4246572
    Abstract: A battery-powered fire alarm including a smoke detector circuit, a controllable horn circuit and a battery monitoring circuit. The smoke detector employs a pair of complementary field-effect transistor switches with gates respectively connected to an ionization chamber and a potentiometer of a Wheatstone bridge circuit connected across the battery. The field-effect transistors are biased off to minimize standby power consumption and are connected such that the threshold voltages thereof are offsetting to minimize supply voltage sensitivity of the detector. When the voltage from the ionization chamber assumes a value approximately equal to a preselected alarm voltage at the potentiometer, both field-effect transistors turn on to energize an alarm circuit to sound an alarm. Hysteresis circuitry is provided to ensure that the complementary switches, once turned on, will not turn off and thereby terminate the alarm until after the alarm condition has terminated.
    Type: Grant
    Filed: March 27, 1978
    Date of Patent: January 20, 1981
    Assignee: Patent Development & Management Company
    Inventor: Larry D. Larsen
  • Patent number: 4083037
    Abstract: A battery-powered fire alarm including a smoke detector, a controllable horn circuit and a battery monitoring circuit. The smoke detector employs a pair of complementary field-effect transistor switches with gates respectively connected to an ionization chamber and a potentiometer of a Wheatstone bridge circuit connected across the battery. The field-effect transistors are biased off to minimize standby power consumption and are connected such that the threshold voltages thereof are offsetting to minimize supply voltage sensitivity of the detector. When the voltage from the ionization chamber assumes a value approximately equal to the potentiometer voltage, both field-effect transistors turn on to energize an alarm circuit to sound an alarm. The switching circuit is provided with hysteresis through positive feedback. The battery monitoring circuit employs a pair of complementary field-effect transistors connected with each other to establish a reference voltage to which the battery voltage is compared.
    Type: Grant
    Filed: December 8, 1975
    Date of Patent: April 4, 1978
    Assignee: Patent Development & Management Company
    Inventor: Larry D. Larsen
  • Patent number: D247665
    Type: Grant
    Filed: February 23, 1976
    Date of Patent: April 4, 1978
    Assignee: Patent Development & Management Company
    Inventor: Larry D. Larsen