Abstract: A three-dimensional (“3-D”) memory capacitor comprises a bottom electrode, a ferroelectric thin film, and a top electrode that conform to a 3-D surface of an insulator layer. The capacitance area is greater than the horizontal footprint area of the capacitor. Preferably, the footprint of the capacitor is less than 0.2 nm2, and the corresponding capacitance area is typically in a range of from 0.4 nm2 to 1.0 nm2 The ferroelectric thin film preferably has a thickness not exceeding 60 nm. A capacitor laminate including the bottom electrode, ferroelectric thin film, and the top electrode preferably has a thickness not exceeding 200 nm. A low-thermal-budget MOCVD method for depositing a ferroelectric thin film having a thickness in a range of from 30 nm to 90 nm includes an RTP treatment before depositing the top electrode and an RTP treatment after depositing the top electrode and etching the ferroelectric layer.

Abstract: A 1T1R resistive memory array comprised of chains of memory cells, where each memory cell is composed of a resistive element in parallel with a switch. Such chains of memory cells are non-volatile and provide for each of the memory cells to be randomly accessed.

Abstract: A nonconductive hydrogen barrier layer is deposited on a substrate and completely covers the surface area over a memory capacitor and a MOSFET switch of an integrated circuit memory cell. A portion of an insulator layer adjacent to the bottom electrode of a memory capacitor is removed by etching to form a moat region. A nonconductive oxygen barrier layer is deposited to cover the sidewall and bottom of the moat. The nonconductive oxygen barrier layer and a conductive diffusion barrier beneath the capacitor together provide a substantially continuous diffusion barrier between the capacitor and a switch. Also, the nonconductive hydrogen barrier layer, the nonconductive oxygen barrier, and the conductive diffusion barrier substantially completely envelop the capacitor, in particular a ferroelectric thin film in the capacitor.

Abstract: A device and method of reading a ferroelectric memory, including providing a ferroelectric memory including a ferroelectric memory cell, a charge integrator, and a bit line connecting the ferroelectric memory cell and the charge integrator. Pulses are applied to the ferroelectric memory cell, where each of the pulses are of a value lower than that which will destroy data stored in the memory cell. Output voltage values from the ferroelectric memory cell are accumulated by the charge integrator in response to each pulse. The output of the charge integrator may be read to determine whether the datum value stored in the memory cell is a logic high or low value. In one embodiment, the output of the charge integrator is read at a predetermined time after starting the pulses.

Abstract: A three-dimensional (“3-D”) memory capacitor comprises a bottom electrode, a ferroelectric thin film, and a top electrode that conform to a 3-D surface of an insulator layer. The capacitance area is greater than the horizontal footprint area of the capacitor. Preferably, the footprint of the capacitor is less than 0.2 nm2, and the corresponding capacitance area is typically in a range of from 0.4 nm2 to 1.0 nm2 The ferroelectric thin film preferably has a thickness not exceeding 60 nm. A capacitor laminate including the bottom electrode, ferroelectric thin film, and the top electrode preferably has a thickness not exceeding 200 nm. A low-thermal-budget MOCVD method for depositing a ferroelectric thin film having a thickness in a range of from 30 nm to 90 nm includes an RTP treatment before depositing the top electrode and an RTP treatment after depositing the top electrode and etching the ferroelectric layer.

Abstract: A hydrogen diffusion barrier in an integrated circuit is located to inhibit diffusion of hydrogen to a thin film of a metal oxide, such as a ferroelectric layered superlattice material, in an integrated circuit. The hydrogen diffusion barrier comprises at least one of the following chemical compounds: strontium tantalate, bismuth tantalate, tantalum oxide, titanium oxide, zirconium oxide and aluminum oxide. The hydrogen barrier layer is amorphous and is made by a MOCVD process at a temperature of 450° C. or less. A supplemental hydrogen barrier layer comprising a material selected from the group consisting of silicon nitride and a crystalline form of one of said hydrogen barrier layer materials is formed adjacent to said hydrogen diffusion barrier.

Abstract: A pyrometer cell comprises a first ferroelectric capacitor, a second ferroelectric capacitor, and a difference circuit for determining the difference between the polarization charge, voltage, or current between the first and second ferroelectric capacitors. The cell is pulsed a plurality of times and an integrator circuit connected to the difference circuit provides an enhanced output signal representative of the integrated difference. An infrared imager is formed by an array of the pyrometer cells, with one ferroelectric capacitor in each cell exposed to an infrared source and the other ferroelectric capacitor not exposed to the infrared source.

Abstract: A non-volatile SRAM memory comprising a plurality of memory cells, each memory cell including a SRAM memory cell portion and a ferroelectric memory cell portion including a ferroelectric element, the ferroelectric memory cell portion including a switch system for permitting the ferroelectric element to be isolated from the ferroelectric elements in all other memory cells.

Abstract: A ferroelectric memory 636 includes a group of memory cells (645, 12, 201, 301, 401, 501), each cell having a ferroelectric memory element (44, 218, etc.), a drive line (122, 322, 422, 522 etc.) on which a voltage for writing information to the group of memory cells is placed, a bit line (25, 49, 125, 325, 425, 525, etc.) on which information to be read out of the group of memory cells is placed, a preamplifier (20, 42, 120, 320, 420, etc.) between the memory cells and the bit line, a set switch (14, 114, 314, 414, 514, etc.) connected between the drive line and the memory cells, and a reset switch (16, 116, 316, 416, 516, etc.) connected to the memory cells in parallel with the preamplifier. The memory is read by placing a voltage less than the coercive voltage of the ferroelectric memory element across a memory element. Prior to reading, noise from the group of cells is discharged by grounding both electrodes of the ferroelectric memory element.

Abstract: Integrated circuit capacitors in which the capacitor dielectric is a thin film of BST having a grain size smaller than 200 nanometers formed above a silicon germanium substrate. Typical grain sizes are 40 nm and less. The BST is formed by deposition of a liquid precursor by a spin-on process. The original liquid precursor includes an alkoxycarboxylate dissolved in 2-methoxyethanol and a xylene exchange is performed just prior to spinning. The precursor is dried in air at a temperature of about 400° C. and then furnace annealed in oxygen at a temperature of between 600° C. and 850° C.

Abstract: A ferroelectric memory (436) includes a plurality of memory cells (73, 82, 100) each containing a ferroelectric thin film (15) including a microscopically composite material having a ferroelectric component (18) and a dielectric component (19), the dielectric component being a different chemical compound than the ferroelectric component. The dielectric component is preferably a fluxor, i.e., a material having a higher crystallization velocity than the ferroelectric component. The addition of the fluxor permits a ferroelectric thin film to be crystallized at a temperature of between 400° C. and 550° C.

Abstract: A plurality of liquids, the flow of each controlled by a volumetric flowrate controller, are mixed in a mixer to form a final precursor that is misted and then deposited on a substrate. A physical property of precursor liquid is adjusted by adjusting the volumetric flowrate controllers, so that when precursor is applied to substrate and treated, the resulting thin film of solid material has a smooth and planar surface. Typically the physical property is the viscosity of the precursor, which is selected to be relatively low, in the range of 1-2 centipoise.

Abstract: A hydrogen diffusion barrier in an integrated circuit is located to inhibit diffusion of hydrogen to a thin film of a metal oxide, such as a ferroelectric layered superlattice material, in an integrated circuit. The hydrogen diffusion barrier comprises at least one of the following chemical compounds: strontium tantalate, bismuth tantalate, tantalum oxide, titanium oxide, zirconium oxide and aluminum oxide. The hydrogen barrier layer is amorphous and is made by a MOCVD process at a temperature of 450° C. or less. A supplemental hydrogen barrier layer comprising a material selected from the group consisting of silicon nitride and a crystalline form of one of said hydrogen barrier layer materials is formed adjacent to said hydrogen diffusion barrier.

Abstract: A precursor for forming a thin film of layered superlattice material is applied to an integrated circuit substrate. The precursor coating is heated using rapid thermal processing (RTP) with a ramping rate of 100° C./second at a hold temperature in a range of from 500° C. to 900° C. for a cumulative heating time not exceeding 30 minutes, and preferably less than 5 minutes. In fabricating a ferroelectric memory cell, the coating is heated in oxygen using RTP, then a top electrode layer is formed, and then the substrate including the coating is heated using RTP in oxygen or in nonreactive gas after forming the top electrode layer. The thin film of layered superlattice material preferably comprises strontium bismuth tantalate or strontium bismuth tantalum niobate, and preferably has a thickness in a range of from 25 nm to 120 nm. The process of fabricating a thin film of layered superlattice material typically has a thermal budget value not exceeding 960,000° C.

Abstract: An integrated circuit includes a layered superlattice material including one or more of the elements cerium, praseodymium, neodymium, promethium, samarium, europium, gadolinium, terbium, dysprosium, holmium, erbium, thulium, ytterbium, and lutetium. These elements may either be A-site elements or superlattice generator elements in the layered superlattice material. In one embodiment, one or more of these elements substitute for bismuth in a bismuth layered material. They also are preferably used in combination with one or more of the following elements: strontium, calcium, barium, bismuth, cadmium, lead, titanium, tantalum, hafnium, tungsten, niobium, zirconium, bismuth, scandium, yttrium, lanthanum, antimony, chromium, thallium, oxygen, chlorine, and fluorine. Some of these materials are ferroelectrics that crystallize at relatively low temperatures and are applied in ferroelectric non-volatile memories.

Abstract: A hydrogen diffusion barrier in an integrated circuit is located to inhibit diffusion of hydrogen to a thin film of a metal oxide, such as a ferroelectric layered superlattice material, in an integrated circuit. The hydrogen diffusion barrier comprises at least one of the following chemical compounds: strontium tantalate, bismuth tantalate, tantalum oxide, titanium oxide, zirconium oxide and aluminum oxide. The hydrogen barrier layer is amorphous and is made by a MOCVD process at a temperature of 450° C. or less. A supplemental hydrogen barrier layer comprising a material selected from the group consisting of silicon nitride and a crystalline form of one of said hydrogen barrier layer materials is formed adjacent to said hydrogen diffusion barrier.

Abstract: A three-dimensional (“3-D”) memory capacitor comprises a bottom electrode, a ferroelectric thin film, and a top electrode that conform to a 3-D surface of an insulator layer. The capacitance area is greater than the horizontal footprint area of the capacitor. Preferably, the footprint of the capacitor is less than 0.2 nm2, and the corresponding capacitance area is typically in a range of from 0.4 nm2 to 1.0 nm2 The ferroelectric thin film preferably has a thickness not exceeding 60 nm. A capacitor laminate including the bottom electrode, ferroelectric thin film, and the top electrode preferably has a thickness not exceeding 200 nm. A low-thermal-budget MOCVD method for depositing a ferroelectric thin film having a thickness in a range of from 30 nm to 90 nm includes an RTP treatment before depositing the top electrode and an RTP treatment after depositing the top electrode and etching the ferroelectric layer.

Abstract: A ferroelectric memory (436) includes a plurality of memory cells (73, 82, 100) each containing a ferroelectric thin film (15) including a microscopically composite material having a ferroelectric component (18) and a dielectric component (19), the dielectric component being a different chemical compound than the ferroelectric component. The dielectric component is preferably a fluxor, i.e., a material having a higher crystallization velocity than the ferroelectric component. The addition of the fluxor permits a ferroelectric thin film to be crystallized at a temperature of between 400° C. and 550° C.

Abstract: A nonconductive hydrogen barrier layer is deposited on a substrate and completely covers the surface area over a memory capacitor and a MOSFET switch of an integrated circuit memory cell. A portion of an insulator layer adjacent to the bottom electrode of a memory capacitor is removed by etching to form a moat region. A nonconductive oxygen barrier layer is deposited to cover the sidewall and bottom of the moat. The nonconductive oxygen barrier layer and a conductive diffusion barrier beneath the capacitor together provide a substantially continuous diffusion barrier between the capacitor and a switch. Also, the nonconductive hydrogen barrier layer, the nonconductive oxygen barrier, and the conductive diffusion barrier substantially completely envelop the capacitor, in particular a ferroelectric thin film in the capacitor.

Abstract: A precursor for forming a thin film of layered superlattice material is applied to an integrated circuit substrate. The precursor coating is heated using rapid thermal processing (RTP) with a ramping rate of 100° C./second at a hold temperature in a range of from 500° C. to 900° C. for a cumulative heating time not exceeding 30 minutes, and preferably less than 5 minutes. In fabricating a ferroelectric memory cell, the coating is heated in oxygen using RTP, then a top electrode layer is formed, and then the substrate including the coating is heated using RTP in oxygen or in nonreactive gas after forming the top electrode layer. The thin film of layered superlattice material preferably comprises strontium bismuth tantalate or strontium bismuth tantalum niobate, and preferably has a thickness in a range of from 25 nm to 120 nm. The process of fabricating a thin film of layered superlattice material typically has a thermal budget value not exceeding 960,000° C.