Abstract: An improved chip topography for a disk memory controller circuit is provided which includes chip buffer circuitry disposed around the periphery of the chip wherein the chip buffer circuitry forms a quadrilateral outer framework on the chip and data I/O buffer circuitry forms a first side of the quadrilateral outer framework; data I/O buffer control circuitry disposed between first and second corners of the chip buffer circuitry and adjacent to the data I/O buffer circuitry; a microcontroller for regulating the functions of the disk memory controller chip wherein a first portion of the microcontroller is disposed adjacent to the data I/O buffer control circuitry and along a part of a second side of the chip buffer circuitry; drive control and unit select registers coupled to the microcontroller and the chip buffer circuitry, and disposed adjacent to the first portion of the microcontroller and along part of a third side and within a third corner of the chip buffer circuitry, said microcontroller further compri

Abstract: An improved chip topography for a disk memory controller circuit is provided which includes electrical interface circuitry disposed around the periphery of the chip and forming an approximately quadrilateral framework surrounding the remainder of the circuitry, a read-only-memory (ROM) disposed in one corner of the interface framework; a microcontroller disposed adjacent to the ROM and along part of a first side of the interface framework; read data processing circuitry disposed adjacent to the microcontroller and within a second corner of the interface framework and along part of a second side thereof; error checking circuitry disposed adjacent to the read data processing circuitry and along part of the second side of the interface framework; the microcontroller also being disposed adjacent to the error checking circuitry and along part of the second side of the interface framework; write data processing circuitry disposed adjacent to the microcontroller along the second side of the interface boundary, withi

Abstract: An optimum chip topography for a MOS LSI Data Encryption Standard (DES) circuit, including interface and input/output circuitry disposed around the periphery of the chip, control circuitry disposed in a substantially rectangular area across the upper one-third of the surface of the chip, and, disposed on approximately the lower two-thirds of the surface of the chip and perpendicular to the control circuitry area, and arranged from one side of the chip to the other side of the chip, a key register, permuted choice circuitry, a first combinatorial circuit, a right data register, a second combinatorial circuit, a left data register, a P-combinatorial circuit, a first programmable logic arry group, and a second programmable logic array group. The bonding pad sequence for the MOS DES circuit chip is selected to allow the chip to be placed in either a 40-pin dual-in-line package or a 28-pin dual-in-line package.