Abstract: An internet router is implemented as a network fabric of fabric routers and links. The internet router receives data packets from trunk lines or other internet links and analyzes header information in the data packets to route the data packets to output internet links. The line interface also analyzes the header to define a fabric path through the router fabric. The internet packets are broken into flits which are transferred through the router according to a wormhole routing protocol. Flits are stored in fabric routers at storage locations assigned to virtual channels corresponding to destination internet links. The virtual channels and links within the fabric define virtual networks in which congestion in one virtual network is substantially nonblocking to data flow through other virtual networks. Arbitration is performed at each fabric router to assign packets to virtual channels and to assign virtual channels to output fabric links.

Abstract: Prefix searches for directing internet data packets are performed in a prefix search integrated circuit. The integrated circuit includes an array of search engines, each of which accesses a prefix search tree data structure to process a prefix search. An SDRAM is dedicated to each search engine, and SDRAMs share address and control pins to plural search engines on the IC chip. Internal nodes of the tree data structure are duplicated across banks of the SDRAMs to increase bandwidth, and leaf nodes are stored across the SDRAM banks to reduce storage requirements. Within each search engine, data stored in a data register from an SDRAM is compared to a prefix search key stored in a key register. Based on that comparison, an address is calculated to access further tree structure data from the SDRAM. Packet descriptors containing search keys are forwarded to the search engines from an input queue and the search results are forwarded to an output queue, the same packet order being maintained in the two queues.

Abstract: A processor, particularly a network processor, is designed by first writing code to be processed by the processor. That code is then electronically compiled to design hardware of the processor and to provide executable code for execution on the designed hardware. To facilitate compilation, the written code may be restricted by predefined functional units to be implemented in hardware, and the executable code may include very long instruction word code. The functional units may be implemented in reconfigurable circuitry or custom circuitry, and the designed hardware may include combinational logic in reconfigurable circuitry.

Abstract: In scheduling a packet, latency requirements of the packet is determined. The packet is then scheduled according to its latency requirements. Queues may be assigned latency ranges and packets are assigned to the queues according to those ranges. Within ranges, queues of different priorities may be provided.

Abstract: Queuing operations are separated into distinct logical blocks despite the need to share information. Preparatory operations such as queue status fetching, correctness check and random early drop operation may be performed in one or more logical blocks and the completion of the queuing operation, either enqueuing, dequeuing or both, may be performed in another logical block. The operations processed in the first logical block may pass information to the operations processed in the second logical block to improve sharing of information.

Abstract: Sort elements, such as queues processed in a network processor, are provided with relative priorities relative to each other. A set of relative priorities is used to specify priority order of the sort elements. The priority order may be specified by addressing code in a jump table. Duplicate code in the jump table having multiple entrance points allows for reduction of the size of the jump table. The relative priorities may be applied to a lookup table, hash or other function in order to address the jump table.

Abstract: In a network router, a tree structure or a sorting network is used to compare scheduling values and select a packet to be forwarded from an appropriate queue. In the tree structure, each leaf represents the scheduling value of a queue and internal nodes of the structure represent winners in comparisons of scheduling values of sibling nodes of the tree structure. CBR scheduling values may first be compared to select a queue and, if transmission from a CBR queue is not timely, a packet may be selected using WFQ scheduling values. The scheduling values are updated to reflect variable packet lengths and byte stuffing in the prior packet. Scheduling may be performed in multiple stages.

Abstract: Paths for packets traveling through a distributed network fabric are chosen using information local to the source of packets. The system allows resequencing of packets at their destination and detecting out-of-order and missing packets.

Abstract: In a fabric router, flits are stored on chip in a first set of rapidly accessible flit buffers, and overflow from the first set of flit buffers is stored in a second set of off-chip flit buffers that are accessed more slowly than the first set. The flit buffers may include a buffer pool accessed through a pointer array or a set associative cache. Flow control between network nodes stops the arrival of new flits while transferring flits between the first set of buffers and the second set of buffers.