Patents by Inventor Larry Jann
Larry Jann has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10083950Abstract: A die stacking method is provided. The die stacking method includes executing a manufacturing recipe, and loading an interposer-die mapping file according to the manufacturing recipe. The interposer-die mapping file corresponds to an interposer wafer including interposer dies. The die stacking method also includes loading a combination setting data according to the interposer-die mapping file, and loading a top die number and a top-die ID code of a top-die mapping file according to the combination setting data and the interposer-die mapping file. The top-die ID code corresponds to a top wafer including top dies, and the top die number corresponds to one of the top dies. The die stacking method also includes disposing the one of the top dies of the top wafer on one of the interposer dies of the interposer wafer.Type: GrantFiled: December 15, 2016Date of Patent: September 25, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Larry Jann, Chih-Chien Chang, Po-Wen Chuang, Ming-I Chiu, Chang-Hsi Lin, Chih-Chan Li, Yi-Ting Hu
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Publication number: 20170098639Abstract: A die stacking method is provided. The die stacking method includes executing a manufacturing recipe, and loading an interposer-die mapping file according to the manufacturing recipe. The interposer-die mapping file corresponds to an interposer wafer including interposer dies. The die stacking method also includes loading a combination setting data according to the interposer-die mapping file, and loading a top die number and a top-die ID code of a top-die mapping file according to the combination setting data and the interposer-die mapping file. The top-die ID code corresponds to a top wafer including top dies, and the top die number corresponds to one of the top dies. The die stacking method also includes disposing the one of the top dies of the top wafer on one of the interposer dies of the interposer wafer.Type: ApplicationFiled: December 15, 2016Publication date: April 6, 2017Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Larry JANN, Chih-Chien CHANG, Po-Wen CHUANG, Ming-I CHIU, Chang-Hsi LIN, Chih-Chan LI, Yi-Ting HU
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Patent number: 9536814Abstract: Embodiments of a die stacking apparatus are provided. The die stacking apparatus includes a storage device configured to contain a top wafer and an interposer wafer. The top wafer has a number of top dies, and the interposer wafer has a number of interposer dies. The die stacking apparatus also includes a carrier device configured to carry the interposer wafer, and a transferring device configured to transfer the interposer wafer to the carrier device and to dispose the top dies on the interposer dies. The die stacking apparatus further includes a process module configured to control the transferring device. The process module controls the transferring device to transfer the interposer wafer to the carrier device, and controls the transferring device to dispose the top dies on the interposer dies of the interposer wafer, which is stacked on the carrier device.Type: GrantFiled: February 24, 2014Date of Patent: January 3, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Larry Jann, Chih-Chien Chang, Po-Wen Chuang, Ming-I Chiu, Chang-Hsi Lin, Chih-Chan Li, Yi-Ting Hu
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Publication number: 20150243630Abstract: Embodiments of a die stacking apparatus are provided. The die stacking apparatus includes a storage device configured to contain a top wafer and an interposer wafer. The top wafer has a number of top dies, and the interposer wafer has a number of interposer dies. The die stacking apparatus also includes a carrier device configured to carry the interposer wafer, and a transferring device configured to transfer the interposer wafer to the carrier device and to dispose the top dies on the interposer dies. The die stacking apparatus further includes a process module configured to control the transferring device. The process module controls the transferring device to transfer the interposer wafer to the carrier device, and controls the transferring device to dispose the top dies on the interposer dies of the interposer wafer, which is stacked on the carrier device.Type: ApplicationFiled: February 24, 2014Publication date: August 27, 2015Applicant: Taiwan Semiconductor Manufacturing Co., LtdInventors: Larry JANN, Chih-Chien CHANG, Po-Wen CHUANG, Ming-I CHIU, Chang-Hsi LIN, Chih-Chan LI, Yi-Ting HU
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Patent number: 7613535Abstract: A semiconductor manufacturing system includes a centralized computer integrated manufacturing (CIM) system; a plurality of sectional CIM systems respectively associated with a plurality of manufacturing facilities and coupled with the centralized CIM system; and a centralized basic record module, coupled and coordinated with the centralized CIM system, and designed for defining a unified process flow associated to a mobile object.Type: GrantFiled: February 14, 2007Date of Patent: November 3, 2009Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Larry Jann, Chien-Fei Cheng, I. Chun Chen, Liang Po Hsiung
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Publication number: 20080109096Abstract: A semiconductor manufacturing system includes a centralized computer integrated manufacturing (CIM) system; a plurality of sectional CIM systems respectively associated with a plurality of manufacturing facilities and coupled with the centralized CIM system; and a centralized basic record module, coupled and coordinated with the centralized CIM system, and designed for defining a unified process flow associated to a mobile object.Type: ApplicationFiled: February 14, 2007Publication date: May 8, 2008Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Larry Jann, Chien-Fei Cheng, I. Chun Chen, Liang Po Hsiung
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Patent number: 7058469Abstract: A computer-implemented method and system for automating control of a furnace area within a semiconductor fabrication facility are provided. In one example, the method includes processing a current batch using process equipment, removing the current batch from the process equipment, and loading a next batch into the process equipment. The current batch may then be tested to determine if the current batch was properly processed. If the current batch fails the testing, the next batch may be removed from the process equipment and corrections may be made to the process equipment before reloading the next batch. If the current batch passes the testing, the next batch may be set as the new current batch and the new current batch may be processed.Type: GrantFiled: June 24, 2004Date of Patent: June 6, 2006Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming Wang, Tsean Chou, Larry Jann
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Patent number: 7039482Abstract: A method to handle operation exceptions in an automated manufacturing system is achieved. The method comprises providing an automated manufacturing system comprising a means to track progress of work in process against standard process flows and a means to select product lots for processing from the work in process and to select equipment for processing the product lots based on next step information from the standard process flows. The automated manufacturing system is monitored for operation exception events. The product lots must deviate from the standard process flows. A floating process flow is selected corresponding to the operation exception event and the product lots from a floating process flow database. The floating process flow is linked to the standard process flow such that the next step is derived from the floating process flow. Manufacturing is continued using the floating process flow.Type: GrantFiled: October 28, 2003Date of Patent: May 2, 2006Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsien-Jung Hsu, Larry Jann
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Publication number: 20050288814Abstract: A computer-implemented method and system for automating control of a furnace area within a semiconductor fabrication facility are provided. In one example, the method includes processing a current batch using process equipment, removing the current batch from the process equipment, and loading a next batch into the process equipment. The current batch may then be tested to determine if the current batch was properly processed. If the current batch fails the testing, the next batch may be removed from the process equipment and corrections may be made to the process equipment before reloading the next batch. If the current batch passes the testing, the next batch may be set as the new current batch and the new current batch may be processed.Type: ApplicationFiled: June 24, 2004Publication date: December 29, 2005Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming Wang, Tse Chou, Larry Jann
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Publication number: 20050192690Abstract: A new solution in 300 mm Chip Probing (CP) Manufacturing Execution System (MES) design based on a SiView infrastructure. It models actual behavior making it possible to specify exact test program and equipment configuration. The test program, product file, and probe card are modeled into the MES infrastructure so that extra systems and tables requiring costly maintenance can be eliminated. With the required tester configuration built into the product class and tester capability status built into the test equipment's properties, real-time lot-equipment dispatching can occur according to the configuration. A modified version can be supported by I-EDA and PCMS.Type: ApplicationFiled: February 26, 2004Publication date: September 1, 2005Inventors: Keng-Chia Yang, Shu-Min Chen, Larry Jann, Lieh-Jung Chen
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Publication number: 20050096782Abstract: A system and method for automated sorter operations including a storage device and a sorting module. The storage device stores multiple process records, each record including an identity and a current status. The sorting module receives a wafer lot identity and acquires the current status from the process record accordingly. The sorting module issues a first status setting instruction to a manufacturing execution system (MES) to release the wafer lot, issues a flow instruction with sorting recipes directing the MES to perform a sorter operation, and issues a second status setting Instruction to the MES to hold or bank the wafer lot.Type: ApplicationFiled: October 30, 2003Publication date: May 5, 2005Inventors: T-Chun Chen, Hsien Hsu, Tse-An Chou, Ming Wang, Larry Jann
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Publication number: 20050090924Abstract: A method to handle operation exceptions in an automated manufacturing system is achieved. The method comprises providing an automated manufacturing system comprising a means to track progress of work in process against standard process flows and a means to select product lots for processing from the work in process and to select equipment for processing the product lots based on next step information from the standard process flows. The automated manufacturing system is monitored for operation exception events. The product lots must deviate from the standard process flows. A floating process flow is selected corresponding to the operation exception event and the product lots from a floating process flow database. The floating process flow is linked to the standard process flow such that the next step is derived from the floating process flow. Manufacturing is continued using the floating process flow.Type: ApplicationFiled: October 28, 2003Publication date: April 28, 2005Inventors: Hsien-Jung Hsu, Larry Jann
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Patent number: 6799909Abstract: A method of providing fully automated processing of a Split Lot of wafers to manufacture semiconductor devices is provided. The method processes a test Lot of wafers with a production Lot. Processing of both Lots continue as a single Lot along the production processing path up to a split condition process. Processing of the production Lot is put on hold until the alternate processing or test Lot processing is completed. The two Lots are then merged and processed according to the original predefined process steps continue on both Lots.Type: GrantFiled: April 4, 2003Date of Patent: October 5, 2004Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih Pang Liu, Hao Ming Gong, Wei Yao Lin, Hsien Jung Hsu, Hsiao Lung Chu, I-Chun Chen, Tse An Chou, Larry Jann
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Publication number: 20040115842Abstract: A method of providing fully automated processing of a Split Lot of wafers to manufacture semiconductor devices is provided. The method processes a test Lot of wafers with a production Lot. Processing of both Lots continue as a single Lot along the production processing path up to a split condition process. Processing of the production Lot is put on hold until the alternate processing or test Lot processing is completed. The two Lots are then merged and processed according to the original predefined process steps continue on both Lots.Type: ApplicationFiled: April 4, 2003Publication date: June 17, 2004Inventors: Chih Pang Liu, Hao Ming Gong, Wei Yao Lin, Hsien Jung Hsu, Hsiao Lung Chu, I-Chun Chen, Tse An Chou, Larry Jann
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Patent number: 6730604Abstract: A method for dynamically maintaining compatible contamination levels of equipment, wafer Lots and FOUP's used for automated processing of a Split Lot of wafers. Processing of the test Lot and the production Lot continue as a single Lot along the production processing path up to a split condition process. Processing of the production Lot is put on hold and its designated contamination level is saved until the alternate processing or test Lot processing is completed. The contamination level of the Split Lot is reevaluated based on the completed process(es) and will be designated at the same level it carried at the Split or a higher contamination level if appropriate. The two Lots are then merged and given the highest contamination level of either the saved level or the Split Lot. The two Lots are then processed according to the original predefined process steps and at the redefined contamination level.Type: GrantFiled: April 4, 2003Date of Patent: May 4, 2004Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih Pang Liu, Hao Ming Gong, Hsien Jung Hsu, I-Chun Chen, Tse An Chou, Larry Jann