Abstract: A boundary scan based VIH/VIL test scheme for a clock forwarded interface of an IEEE 1149.1 Standard-compliant electronic component is provided. The Standard-compliant component has a test access port (TAP) and a forwarded clock interface including data and forwarded clock inputs for receiving signals from and sending signals to external circuitry during a test operation. Connected to each of such component's data inputs is a clocked and an unclocked input buffer. Coupled to the TAP is an instruction register for receiving Standard defined and other test instructions provided by the external circuitry at the TAP. Also coupled to the TAP is a chain of boundary scan cells, each associated with a different one of the input pins and connected to the output of each input buffer coupled thereto, and a TAP controller for generating control signals to capture and shift data through the boundary scan cells in response to test instructions received by the instruction register.

Abstract: In a method for improving a circuit having a logically false path through static analysis of a software model, a computer receives information describing the false path, determines a true path alternate to the false path, and analyses the circuit model with respect to the true path.

Abstract: A method for performing integrated section-level and full-chip timing verification is employed for integrated circuit designs that include several section designs. A plurality of bristle timing parameters define timing relationships between the section designs. A section-level verification procedure is performed for each of the section designs to determine whether the section designs conform to predetermined intra-section timing constraints. A full-chip verification procedure is performed for the integrated circuit design to determine the bristle timing parameters and to determine whether the integrated circuit design conforms with predetermined intersection timing constraints.

Abstract: In a pipelined digital computer, an instruction decoder decodes register specifiers from multiple instructions, and stores them in a source queue and a destination queue. An execution unit successively obtains source specifiers of an instruction from the source queue, initiates an operation upon the source specifiers, reads a destination specifier from the destination queue, and retires the result at the specified destination. Read-after-write conflicts may occur because the execution unit may overlap execution of a plurality of instructions. Just prior to beginning execution of a current instruction, the destination queue is checked for conflict between the source specifiers of the current instruction and the destination specifiers of previously issued but not yet retired instructions. When an instruction is issued for execution, its destination specifiers in the destination queue are marked to indicate that they are associated with an executed but not yet retired instruction.