Abstract: An automatic test system controlled by a general purpose digital central processor is disclosed. The central processor accepts test programs in a high level compiler language such as Atlas. The Atlas program is compacted into a simplified language which is utilized to communicate with test devices via a standard IEEE 488 data bus. Each of the test devices includes a programmable interface digital processor which performs any translation that may be necessary in order to permit specific test instruments coupled to the central processor via the interface processor to perform the tests specified by the high level test programs. A switching matrix also communicates with the digital processor to connect the appropriate test device to the unit under test.

Abstract: An interface circuit for coupling a digital processor to a core memory. The interface circuit accepts as inputs address signals, data signals, and control signals from the processor and output date from the core memory. The output of the interface circuit consists of control signals to control the memory and a parallel digital data word having 2N bits where N is the number of parallel bits transferred by the digital processor during the execution of an instruction to transfer data to or input data from an external device. To store a digital data word in a particular location in the core memory, the digital processor first transfers a digital data word having N bits to a buffer memory which is a part of the interface circuit. Next, the digital processor executes a store in memory instruction.