Patents by Inventor Larry Lam

Larry Lam has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7013028
    Abstract: An editor in a computer system for editing an schematic having a number of pages. The editor may cut a selected portion of the schematic from any one of the schematic pages, paste the cut portion of the schematic onto any one of the schematic pages, and connect nets located on the same schematic page. The editor may search for objects such as signal labels and cells within the schematic netlist as well as other editing functions. Further a navigator is provided for interactively viewing netlist data from a high level schematic where the data includes schematic page numbers, cell names, nets, signal labels and segments. The project viewer software and project schematic netlist data may be contained in a computer-readable medium. The project viewer software controls output schematic images and enables a user to view, trace and search objects throughout the project netlist data.
    Type: Grant
    Filed: August 3, 2001
    Date of Patent: March 14, 2006
    Assignee: Semiconductor Insights Inc.
    Inventors: Val Gont, Jason Abt, Larry Lam
  • Patent number: 6738957
    Abstract: A process in a computer system for generating a high level schematic from a project schematic of basic components which comprises scanning the project schematic for a predetermined cell, wherein the cell is made up of a select group of components and their interconnections, and replacing the select group of components on every occurrence that it is found in the project schematic by a cell symbol having input and outputs to generate the high level schematic. The process may also be repeated for other predetermined cells which may be selected from a library or created by the user.
    Type: Grant
    Filed: August 3, 2001
    Date of Patent: May 18, 2004
    Assignee: Semiconductor Insights Inc.
    Inventors: Val Gont, Jason Abt, Larry Lam, Alexei Ioudovski
  • Publication number: 20020023107
    Abstract: A process in a computer system for generating a high level schematic from a project schematic of basic components which comprises scanning the project schematic for a predetermined cell, wherein the cell is made up of a select group of components and their interconnections, and replacing the select group of components on every occurrence that it is found in the project schematic by a cell symbol having input and outputs to generate the high level schematic. The process may also be repeated for other predetermined cells which may be selected from a library or created by the user.
    Type: Application
    Filed: August 3, 2001
    Publication date: February 21, 2002
    Applicant: Semiconductor Insights Inc.
    Inventors: Val Gont, Jason Abt, Larry Lam, Alexei Ioudovski
  • Publication number: 20020018583
    Abstract: An editor in a computer system for editing an schematic having a number of pages. The editor may cut a selected portion of the schematic from any one of the schematic pages, paste the cut portion of the schematic onto any one of the schematic pages, and connect nets located on the same schematic page. The editor may search for objects such as signal labels and cells within the schematic netlist as well as other editing functions. Further a navigator is provided for interactively viewing netlist data from a high level schematic where the data includes schematic page numbers, cell names, nets, signal labels and segments. The project viewer software and project schematic netlist data may be contained in a computer-readable medium. The project viewer software controls output schematic images and enables a user to view, trace and search objects throughout the project netlist data.
    Type: Application
    Filed: August 3, 2001
    Publication date: February 14, 2002
    Applicant: Semiconductor Insights Inc.
    Inventors: Val Gont, Jason Abt, Larry Lam
  • Patent number: 6289116
    Abstract: A method for extracting design information from a semiconductor integrated circuit (IC) or at least a portion thereof comprising the steps of: (a) imaging at least a portion of one or more IC layers to obtain stored images of said portions of the IC; (b) using manual or automatic registration techniques to mosaic images; (c) using an IC layout package possessing a feature of allowing images to be displayed and moved and polygons to be created to allow the recreation of the IC layout in the form of polygons; (d) exporting or storing of a polygon database in a standard IC layout format; (e) creating a table of transistor connections (netlist); (f) organizing circuit netlist into functional blocks of increasing complexity; and (g) generating a schematic diagram.
    Type: Grant
    Filed: September 26, 1997
    Date of Patent: September 11, 2001
    Assignee: Semiconductor Insights, Inc.
    Inventors: George Chamberlain, Larry Lam
  • Patent number: 5694481
    Abstract: A method of analyzing at least a portion of an integrated circuit (IC) comprised of the steps of automatically: (a) scanning at least a portion of a layer of an integrated circuit using high magnification to provide first digital signals representing pixel amplitudes, (b) extracting features of interest from the first digital signals to provide second digital signals representing values of groups of pixels defining the features of interest, (c) modifying the second digital signals representing adjacent features of interest from step (b) so as to mosaic the features of interest and providing third signals representing a seamless representation of the layer, (d) repeating steps (a), (b) and (c) for other layers of the integrated circuit, whereby plural third signals representing plural ones of the layers are provided, (e) registering the plural third signals relative to each other so as to represent vertical alignment of the layers by determining features of interest representative of IC mutual interconnection
    Type: Grant
    Filed: April 12, 1995
    Date of Patent: December 2, 1997
    Assignee: Semiconductor Insights Inc.
    Inventors: Larry Lam, George Chamberlain, Alexei Ioudovsky, Ghassan Naim