Abstract: An electronic messaging system for both participating institutions and nonparticpating institutions and their populations. When an institution is participating in the system of the present invention, both message senders and recipients are authenticated and known and verified before any communication can take place. Messages for institutions not currently participating in the system are converted to printed mail for delivery to the non-participating institution using traditional postal systems. The present invention also teaches novel message processing techniques that take advantage of the electronic format of the messages to provide automated security and translation and/or transliteration services and further teaches the novel feature of marking incoming messages with a code to assist in accurately and secure delivery of reply messages to the appropriate party.

Abstract: An electronic messaging system for both participating institutions and nonparticpating institutions and their populations. When an institution is participating in the system of the present invention, both message senders and recipients are authenticated and known and verified before any communication can take place. Messages for institutions not currently participating in the system are converted to printed mail for delivery to the non-participating institution using traditional postal systems. The present invention also teaches novel message processing techniques that take advantage of the electronic format of the messages to provide automated security and translation and/or transliteration services and further teaches the novel feature of marking incoming messages with a code to assist in accurately and secure delivery of reply messages to the appropriate party.

Abstract: Hardware and software techniques for interrupt detection and response in a scalable pipelined array processor environment are described. Utilizing these techniques, a sequential program execution model with interrupts can be maintained in a highly parallel scalable pipelined array processing containing multiple processing elements and distributed memories and register files. When an interrupt occurs, interface signals are provided to all PEs to support independent interrupt operations in each PE dependent upon the local PE instruction sequence prior to the interrupt. Processing/element exception interrupts are supported and low latency interrupt processing is also provided for embedded systems where real time signal processing is required. Further, a hierarchical interrupt structure is used allowing a generalized debug approach using debut interrupts and a dynamic debut monitor mechanism.