Abstract: A patient treatment system includes a communications module coupled to a communication network, an agreement signification device for capturing data indicative of a signature of a patient, a sensor for monitoring parameters associated with medical equipment prescribed for treatment of the patient, and a microcontroller coupled with the communications module and the sensor.

Abstract: A patient treatment system includes a network server, an agreement signification device, a global positioning system device, and a network-enabled sensor that performs operations including obtaining, using the agreement signification device, global positioning system device, and network-enabled sensor, information that is input into the network server and is associated with at least one of a patient, medical equipment, a physician, and an ancillary provider. The information includes a signature of the patient representing agreement of the patient with data entered by the physician including (1) whether the patient is benefitting from use of the medical equipment, (2) whether the patient needs to continue use of the medical equipment, and (3) hours of operation of the medical equipment. The operations also include coupling the medical equipment to the network-enabled sensor.

Abstract: A method of complying with rules to reduce fraudulent reimbursement associated with durable medical equipment prescriptions includes obtaining, using a processing device, information associated with at least one of a patient, the durable medical equipment, a physician, and an ancillary provider; and providing, using the processing device, selective access to the information. The access is selectively provided to at least one of the physician, ancillary provider, a payor, and an auditor, whereby the selective access enables compliance with the rules to reduce fraudulent reimbursement associated with the durable medical equipment prescriptions. A corresponding computer-readable medium and system are also disclosed.

Abstract: A method for manufacturing a power transistor circuit includes securing a die to a substrate, the die comprising a transistor having an input terminal and an output terminal. One or more performance characteristics of the transistor are measured. Using one or more wire sets, the transistor input terminal is electrically connected to one or more input matching elements and an input signal lead. The impedance of the one or more wire sets, as determined by selecting a desired number and/or length of the wires in each set, is selected based at least in part on the measured transistor performance characteristic(s). Similarly, using one or more additional wire sets, the transistor output terminal is electrically connected to one or more output matching elements and an output signal lead, wherein the impedance of the additional wire sets is selected based at least in part on the measured transistor performance characteristic(s).

Abstract: A laterally diffused metal oxide semiconductor (LDMOS) power package includes a conductive mounting flange mounted on a heat sink and electrically connected to a dielectric substrate of a printed circuit board. A plurality of transistors are mounted on the top surface of the mounting flange. Each of the transistors has an input terminal, an output terminal, and a ground terminal, with the ground terminal of each transistor being electrically coupled to the top surface of the mounting flange. A plurality of parallel ground signal return paths are provided to electrically couple the top surface of the mounting flange to the dielectric substrate, thereby reducing resistance and inductance in the ground signal path and increasing the efficiency of the power package.

Abstract: Conventional broadband RF power amplifiers use a ¼ wavelength transmission line to decouple the gate bias DC source from the gate circuitry and a second ¼ wavelength transmission line to decouple the drain bias DC source from the drain circuitry, taking up considerable printed circuit board space. A novel broadband RF power amplifier uses a transistor with separate terminals for injection of gate bias and drain bias DC sources, eliminating the need for ¼ wavelength transmission lines, thereby freeing up space and allowing higher density packaging. The power amplifier transistor can be implemented with a single die circuit or multiple die circuits operating in parallel.

Abstract: A broadband RF signal amplifier includes a plurality of transistors attached to a surface of a pedestal, each transistor having an input and an output. An RF input path electrically connected to the transistor inputs includes a passive splitter implemented in a multi-layer printed circuit board and configured to split a RF input signal into a plurality of component input signals. A plurality of corresponding input matching networks including one-quarter wavelength transmission lines implemented in the printed circuit board couple respective component input signals to the transistor inputs at an input impedance, the input matching networks further comprising respective input matching capacitors attached to the pedestal. An RF output path electrically connected to the transistor outputs includes a passive combiner implemented in the printed circuit board and configured to combine component output signals received at the transistor outputs into a RF output signal.

Abstract: A multistage power amplifier circuit with superior isolation between gain stages provides alternative common lead currents paths from the individual gain stage elements to obtain improved stability and operational performance.

Abstract: A broadband RF signal amplifier includes a plurality of transistors attached to a surface of a pedestal, each transistor having an input and an output. An RF input path electrically connected to the transistor inputs includes a passive splitter implemented in a multi-layer printed circuit board and configured to split a RF input signal into a plurality of component input signals. A plurality of corresponding input matching networks including one-quarter wavelength transmission lines implemented in the printed circuit board couple respective component input signals to the transistor inputs at an input impedance, the input matching networks further comprising respective input matching capacitors attached to the pedestal. An RF output path electrically connected to the transistor outputs includes a passive combiner implemented in the printed circuit board and configured to combine component output signals received at the transistor outputs into a RF output signal.

Abstract: A tunable impedance matching circuit is provided for tuning an active device, such as, e.g., a field effect transistor, in a RF power amplifier circuit. The matching circuit includes an adjustable length transmission line for electrically coupling a RF signal between an active device and its source and a load. The transmission line, which has a length approximately equal to a quarter of a wavelength of the fundamental frequency of a RF signal being amplified, is adjusted to achieve selected performance characteristic(s) of the amplifier, such as, e.g., input return loss.

Abstract: A push-pull transistor chip comprises a single a semiconductor die having first and second LDMOS transistors formed thereon and configured for push-pull operation, the first and second transistors sharing a common element current region. In a power transistor package, the push-pull transistor chip is attached to a mounting flange serving as a common element ground reference, wherein a conductor (e.g., one or more bond wires) electrically connects the shared common element current region to the mounting flange.

Abstract: A laterally diffused metal oxide semiconductor (LDMOS) power package includes a conductive mounting flange mounted on a heat sink and electrically connected to a dielectric substrate of a printed circuit board. A plurality of transistors are mounted on the top surface of the mounting flange. Each of the transistors has an input terminal, an output terminal, and a ground terminal, with the ground terminal of each transistor being electrically coupled to the top surface of the mounting flange. A plurality of parallel ground signal return paths are provided to electrically couple the top surface of the mounting flange to the dielectric substrate, thereby reducing resistance and inductance in the ground signal path and increasing the efficiency of the power package.

Abstract: A method for manufacturing a power transistor circuit includes securing a die to a substrate, the die comprising a transistor having an input terminal and an output terminal. One or more performance characteristics of the transistor are measured. Using one or more wire sets, the transistor input terminal is electrically connected to one or more input matching elements and an input signal lead. The impedance of the one or more wire sets, (as determined by selecting a desired number and/or length of the wires in each set, is selected based at least in part on the measured transistor performance characteristic(s). Similarly, using one or more additional wire sets, the transistor output terminal is electrically connected to one or more output matching elements and an output signal lead, wherein the impedance of the additional wire sets is selected based at least in part on the measured transistor performance characteristic(s).

Abstract: A push-pull transistor chip comprises a single/semiconductor die having first and second LDMOS transistors formed thereon and configured for push-pull operation, the first and second transistors sharing a common element current region. In a power transistor package, the push-pull transistor chip is attached to a mounting flange serving as a common element ground reference, wherein a conductor (e.g., one or more bond wires) electrically connects the shared common element current region to the mounting flange.

Abstract: A multistage power amplifier circuit with superior isolation between gain stages provides alternative common lead currents paths from the individual gain stage elements to obtain improved stability and operational performance.

Abstract: A packaged integrated circuit device includes a substrate including a first circuit component mounted thereon, a first conductor extending from the first circuit component, and a dielectric lid. The dielectric lid includes a component mounting surface, a second circuit component mounted on the component mounting surface, and a second conductor extending from the second circuit component. The dielectric lid is adapted to engage with the substrate such that the first circuit component is in electrical communication with the second circuit component. The second circuit component may comprises an impedance matching circuit. The circuit device may also include fastening means for securing the lid to the substrate. The fastening means may comprise an adhesive, solder, or a spring biased member.

Abstract: The present invention, generally speaking, provides an apparatus and method whereby the current flow through an RF power transistor may be monitored without the use of any external parts. More particularly, in accordance with one embodiment of the invention, an RF power transistor includes a silicon die, a pair of interdigitated electrodes formed on the silicon die, each having a multiplicity of parallel electrode fingers and at least one bond pad. Regions of a first type of diffusion are formed beneath electrode fingers of one electrode of the pair of interdigitated electrodes, and regions of a second type of diffusion are formed beneath electrode fingers of another electrode of the pair of interdigitated electrodes. One electrode has multiple electrode fingers and multiple resistors formed on the silicon die, at least one resistor connected in series with each one of the electrode fingers.

Abstract: An RF power transistor package is configured for mounting to a heat sink in a multi-layer pc board, and includes a direct top side electrical ground path from a transistor chip located atop a ceramic substrate to a mounting flange, without passing through the ceramic substrate by way of metal plating an outer surface of the ceramic substrate to electrically connect a top mounted metal lead to the flange. A direct ground path from the transistor chip to the mounting flange is also provided by way of plated via holes through the ceramic substrate. The top side ground path is also configured to connect with the middle ground reference layer of the multi-layer pc board when the mounting flange is secured to the heat sink, so that a unified ground potential is seen by the transistor at both the middle layer and heat sink.

Abstract: An RF power transistor having improved thermal balance characteristics includes a first emitter electrode and a base electrode formed on a silicon die, each having a multiplicity of parallel electrode fingers. A second emitter electrode is formed over the base electrode, and is electrically connected to the first emitter electrode. Ballast resistors are formed in a substantially evenly spaced manner on each side the silicon die, in series with at least some of the electrode fingers of the first emitter electrode and in series of at least some of the electrode fingers of the second emitter electrode.

Abstract: An apparatus and method are provided for bypassing the emitter ballast resistors of a power transistor, thereby increasing transistor gain. In a power transistor of the interdigitated type, bypassing the emitter ballast resistors requires bypassing each individual ballast resistor with a capacitor in parallel. Bypassing is therefore done on the silicon chip. More particularly, in accordance with one embodiment of the invention, an RF power transistor includes a silicon die, an emitter ballast resistor formed on the silicon die, and a bypass capacitor formed on the silicon die and connected in parallel with the emitter ballast resistor. The resistor may be a diffused resistor, and the capacitor may be a metal-on-polysilicon capacitor.