Patents by Inventor Larry Leitner
Larry Leitner has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11301392Abstract: A method and an information handling system having a plurality of processors connected by a cross-processor network, where each of the plurality of processors preferably has a filter construct having an outgoing filter list that identifies logical partition identifications (LPIDs) that are exclusively assigned to that processor and/or an incoming filter list that identifies LPIDs on that processor and at least one additional processor in the system. In operation, if the LPID of the outgoing translation invalidation instruction is on the outgoing filter list, the address translation invalidation instruction is acknowledged on behalf of the system. If the LPID of the incoming invalidation instruction does not match any LPID on the incoming filter list, then the translation invalidation instruction is acknowledged, and if the LPID of the incoming invalidation instruction matches any LPID on the incoming filter list, then the invalidation instruction is sent into the respective processor.Type: GrantFiled: October 6, 2020Date of Patent: April 12, 2022Assignee: International Business Machines CorporationInventors: Debapriya Chatterjee, Bryant Cockcroft, Larry Leitner, John A. Schumann, Karen Yokum
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Patent number: 11243864Abstract: An instruction may be associated with a memory address. During execution of the instruction, the memory address may be translated to a next level memory address. The instruction may also be marked for address tracing. If the instruction is marked for address tracing, then during execution of the instruction, the memory address and the next level memory address may be recorded.Type: GrantFiled: September 17, 2019Date of Patent: February 8, 2022Assignee: International Business Machines CorporationInventors: Bryant Cockcroft, John A. Schumann, Debapriya Chatterjee, Larry Leitner, Kevin Barnett, Karen Yokum
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Patent number: 11080122Abstract: Examples described herein provide a computer-implemented method that includes executing, by the microprocessor, instructions in an instruction stream of the microprocessor. The method further includes triggering, by control logic of the microprocessor, error condition monitoring logic. The method further includes executing, by the error condition monitoring logic of the microprocessor, an error instruction stream built into the microprocessor to break the microprocessor out of an error condition.Type: GrantFiled: September 19, 2019Date of Patent: August 3, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Larry Leitner, John A. Schumann, Debapriya Chatterjee, Wallace Sharp, Bryant Cockcroft
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Publication number: 20210089382Abstract: Examples described herein provide a computer-implemented method that includes executing, by the microprocessor, instructions in an instruction stream of the microprocessor. The method further includes triggering, by control logic of the microprocessor, error condition monitoring logic. The method further includes executing, by the error condition monitoring logic of the microprocessor, an error instruction stream built into the microprocessor to break the microprocessor out of an error condition.Type: ApplicationFiled: September 19, 2019Publication date: March 25, 2021Inventors: Larry Leitner, John A. Schumann, Debapriya Chatterjee, Wallace Sharp, Bryant Cockcroft
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Publication number: 20210081296Abstract: An instruction may be associated with a memory address. During execution of the instruction, the memory address may be translated to a next level memory address. The instruction may also be marked for address tracing. If the instruction is marked for address tracing, then during execution of the instruction, the memory address and the next level memory address may be recorded.Type: ApplicationFiled: September 17, 2019Publication date: March 18, 2021Inventors: Bryant Cockcroft, John A. Schumann, Debapriya Chatterjee, Larry Leitner, Kevin Barnett, Karen Yokum
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Patent number: 10915456Abstract: A method and an information handling system having a plurality of processors connected by a cross-processor network, where each of the plurality of processors preferably has a filter construct having an outgoing filter list that identifies logical partition identifications (LPIDs) that are exclusively assigned to that processor and/or an incoming filter list that identifies LPIDs on that processor and at least one additional processor in the system. In operation, if the LPID of the outgoing translation invalidation instruction is on the outgoing filter list, the address translation invalidation instruction is acknowledged on behalf of the system. If the LPID of the incoming invalidation instruction does not match any LPID on the incoming filter list, then the translation invalidation instruction is acknowledged, and if the LPID of the incoming invalidation instruction matches any LPID on the incoming filter list, then the invalidation instruction is sent into the respective processor.Type: GrantFiled: May 21, 2019Date of Patent: February 9, 2021Assignee: International Business Machines CorporationInventors: Debapriya Chatterjee, Bryant Cockcroft, Larry Leitner, John A. Schumann, Karen Yokum
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Publication number: 20210019262Abstract: A method and an information handling system having a plurality of processors connected by a cross-processor network, where each of the plurality of processors preferably has a filter construct having an outgoing filter list that identifies logical partition identifications (LPIDs) that are exclusively assigned to that processor and/or an incoming filter list that identifies LPIDs on that processor and at least one additional processor in the system. In operation, if the LPID of the outgoing translation invalidation instruction is on the outgoing filter list, the address translation invalidation instruction is acknowledged on behalf of the system. If the LPID of the incoming invalidation instruction does not match any LPID on the incoming filter list, then the translation invalidation instruction is acknowledged, and if the LPID of the incoming invalidation instruction matches any LPID on the incoming filter list, then the invalidation instruction is sent into the respective processor.Type: ApplicationFiled: October 6, 2020Publication date: January 21, 2021Inventors: Debapriya Chatterjee, Bryant Cockcroft, Larry Leitner, John A. Schumann, Karen Yokum
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Publication number: 20200371951Abstract: A method and an information handling system having a plurality of processors connected by a cross-processor network, where each of the plurality of processors preferably has a filter construct having an outgoing filter list that identifies logical partition identifications (LPIDs) that are exclusively assigned to that processor and/or an incoming filter list that identifies LPIDs on that processor and at least one additional processor in the system. In operation, if the LPID of the outgoing translation invalidation instruction is on the outgoing filter list, the address translation invalidation instruction is acknowledged on behalf of the system. If the LPID of the incoming invalidation instruction does not match any LPID on the incoming filter list, then the translation invalidation instruction is acknowledged, and if the LPID of the incoming invalidation instruction matches any LPID on the incoming filter list, then the invalidation instruction is sent into the respective processor.Type: ApplicationFiled: May 21, 2019Publication date: November 26, 2020Inventors: Debapriya Chatterjee, Bryant Cockcroft, Larry Leitner, John A. Schumann, Karen Yokum
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Publication number: 20060184840Abstract: A mechanism is provided for determining a cause of a primary error in a complex communications topology without clockstop. A time of day register, or another synchronized register, is provided in each node of the topology for another existing purpose. When an error is encountered, a copy of the register is captured and frozen. The node with the lowest value in the register is determined to be the node that saw the error first. With the copy of the register frozen, the system can continue to function using the time of day register. For the case of determining the cause of primary error for system checkstop only, the actual register may be frozen, providing a solution without requiring the addition of latches to the design.Type: ApplicationFiled: February 11, 2005Publication date: August 17, 2006Applicant: International Business Machines CorporationInventors: Michael Floyd, Larry Leitner
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Publication number: 20060184771Abstract: A method in a data processing system for avoiding a microprocessor's design defects and recovering a microprocessor from failing due to design defects, the method comprised of the following steps: The method detects and reports of events which warn of an error. Then the method locks a current checkpointed state and prevents instructions not checkpointed from checkpointing. After that, the method releases checkpointed state stores to a L2 cache, and drops stores not checkpointed. Next, the method blocks interrupts until recovery is completed. Then the method disables the power savings states throughout the processor. After that, the method disables an instruction fetch and an instruction dispatch. Next, the method sends a hardware reset signal. Then the method restores selected registers from the current checkpointed state. Next, the method fetches instructions from restored instruction addresses. Then the method resumes a normal execution after a programmable number of instructions.Type: ApplicationFiled: February 11, 2005Publication date: August 17, 2006Applicant: International Business MachinesInventors: Michael Floyd, Larry Leitner, Sheldon Levenstein, Scott Swaney, Brian Thompto
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Publication number: 20060184770Abstract: In a processor, a localized workaround is activated upon the sensing of a problematic condition occurring on said processor, and then control of the deactivation of the localized workaround is superseded by a centralized controller. In a preferred embodiment, the centralized controller monitors forward progress of the processor and maintains the workaround in an active condition until a threshold level of forward progress has occurred. Optionally, the localized workaround may be re-activated while under centralized control, resetting the notion of forward progress. Using the present invention, localized workarounds perform effectively while having a minimal impact on processor performance.Type: ApplicationFiled: February 12, 2005Publication date: August 17, 2006Applicant: International Business Machines CorporationInventors: James Bishop, Michael Floyd, Hung Le, Larry Leitner, Brian Thompto
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Publication number: 20060184832Abstract: A trace array with added width is provided. Each trace array entry includes a data portion and a side counter portion. When a programmable subset of trace data repeats, a side counter is incremented. When the programmable subset of the trace data stops repeating, the trace data and the side counter value are stored in the trace array. The trace array may also include a larger counter. In this implementation, if the smaller side counter reaches its maximum value, a larger counter may begin counting. The larger counter value may then be stored in its own trace array entry instead of the trace data. A predetermined side counter value may mark the entry as a larger compression counter instead of as a data entry.Type: ApplicationFiled: February 11, 2005Publication date: August 17, 2006Applicant: International Business Machines CorporationInventors: Michael Floyd, Larry Leitner
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Publication number: 20060184769Abstract: Localized generation of global flush requests while providing a means for increasing the likelihood of forward progress in a controlled fashion. Local hazard (error) detection is accomplished with a trigger network situated between execution units and configurable state machines that track trigger events. Once a hazardous state is detected, a local detection mechanism requests a workaround flush from the flush control logic. The processor is flushed and a centralized workaround control is informed of the workaround flush. The centralized control blocks subsequent workaround flushes until forward progress has been made. The centralized control can also optionally send out a control to activate a set of localized workarounds or reduced performance modes to avoid the hazardous condition once instructions are re-executed after the flush until a configurable amount of forward progress has been made.Type: ApplicationFiled: February 11, 2005Publication date: August 17, 2006Applicant: International Business Machines CorporationInventors: Michael Floyd, Hung Le, Larry Leitner, Brian Thompto
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Publication number: 20060179251Abstract: In a multiprocessor environment, by executing cache-inhibited reads or writes to registers, a scan communication is used to rapidly access registers inside and outside a chip originating the command. Cumbersome locking of the memory location may be thus avoided. Setting of busy latches at the outset virtually eliminates the chance of collisions, and status bits are set to inform the requesting core processor that a command is done and free of error, if that is the case.Type: ApplicationFiled: February 10, 2005Publication date: August 10, 2006Applicant: International Business Machines CorporationInventors: James Fields, Michael Floyd, Paul Lecocq, Larry Leitner, Kevin Reick
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Publication number: 20060179289Abstract: Monitoring is performed to detect a hang condition. A timer is set to detect a hang based on a core hang limit. If a thread hangs for the duration of the core hang limit, then a core hang is detected. If the thread is performing an external memory transaction, then the timer is increased to a longer memory hang limit. If the thread is waiting for a shared resource, then the timer may be increased to the longer memory hang limit if another thread or, more particularly, the thread blocking the resource has a pending memory transaction. Responsive to detecting a hang condition, instructions dispatched to the plurality of execution units may be flushed, or the processor may be reset and restored to a previously known good, checkpointed architected state.Type: ApplicationFiled: February 10, 2005Publication date: August 10, 2006Applicant: International Business Machines CorporationInventors: Michael Floyd, Larry Leitner