Patents by Inventor Larry Lin

Larry Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140056543
    Abstract: The present invention provides a bag made of a non-woven biodegradable material comprising a body portion having at least one side wall and a bottom joined together to define a storage space therebetween and an opening at the top of the body portion, wherein the bag is biodegradable and non-toxic to the environment
    Type: Application
    Filed: January 16, 2011
    Publication date: February 27, 2014
    Applicant: BECAUSE WE CARE PTY LTD
    Inventors: Kenny Lay, Larry Lin
  • Patent number: 6010928
    Abstract: A high density transistor component and its manufacturing method which includes the steps of forming a pad oxide layer above a silicon substrate, forming a dielectric layer above the pad oxide layer, and growing an epitaxial silicon layer above the pad oxide layer covering the pad oxide layer as well as the dielectric layer. Source/drain regions including the heavily doped source/drain and the lightly doped source/drain are formed in the epitaxial silicon layer, and a gate terminal region composed from an assembly of a gate oxide layer, a gate terminal and two spacers is formed above the epitaxial silicon layer. The channel is located in the spatial location between the dielectric layer, the gate region and the source/drain regions.
    Type: Grant
    Filed: April 21, 1998
    Date of Patent: January 4, 2000
    Assignee: United Microelectronics Corp.
    Inventors: Chen-Chung Hsu, Larry Lin
  • Patent number: 5959331
    Abstract: A high density transistor component and its manufacturing method which includes the steps of forming a pad oxide layer above a silicon substrate, forming a dielectric layer above the pad oxide layer, and growing an epitaxial silicon layer above the pad oxide layer covering the pad oxide layer as well as the dielectric layer. Source/drain regions including the heavily doped source/drain and the lightly doped source/drain are formed in the epitaxial silicon layer, and a gate terminal region composed from an assembly of a gate oxide layer, a gate terminal and two spacers is formed above the epitaxial silicon layer. The channel is located in the spatial location between the dielectric layer, the gate region and the source/drain regions.
    Type: Grant
    Filed: August 26, 1997
    Date of Patent: September 28, 1999
    Assignee: United Micorelectronics Corp.
    Inventors: Chen-Chung Hsu, Larry Lin
  • Patent number: 5851910
    Abstract: A method of fabricating a bonding pad window, includes providing a substrate, which is metallized with a first metallization layer; forming a dielectric layer over the first metallization layer; defining the dielectric layer with a first mask to form a via; forming a plug in the via; forming a second metallization layer over the plug and the dielectric layer; patterning the second metallization layer to expose the dielectric layer; forming a passivation layer over the second metallization layer; and defining the passivation layer with the first mask to form the bonding pad window. This improves and simplifies the formation of a bonding pad window. For example, the process of forming a mask, which is used to form the bonding pad window, can be omitted. The previous via mask is used to form the bonding pad window and the internal circuit probing window at the same time.
    Type: Grant
    Filed: September 11, 1997
    Date of Patent: December 22, 1998
    Assignee: United Microelectronics Corp.
    Inventors: Chen-Chung Hsu, Larry Lin
  • Patent number: 5700711
    Abstract: A shield structure is formed over each of the undoped or lightly doped polysilicon load devices of a 4T SRAM cell. The shield structure may be a metal such as aluminum, titanium or tungsten and serves to protect the undoped or lightly doped resistor within a polysilicon load device from charge-induced damage during ion implantation or plasma processing steps performed on the SRAM after formation of the polysilicon load device. The polysilicon load device is defined by depositing a layer of photoresist, exposing the photoresist through a master load mask, etching, and implanting into the exposed polysilicon. After the load device is formed, a dielectric layer is deposited and then a layer of conductive material is deposited. Dummy conductor structures are formed from the layer of conductive material using photolithography and the master load mask.
    Type: Grant
    Filed: October 22, 1996
    Date of Patent: December 23, 1997
    Assignee: United Microelectronics Corporation
    Inventors: Chen-Chung Hsu, Tsun-Tsai Chang, Larry Lin