Abstract: A single chip large scale integration processor possesses its own on-chip control storage array while including the ability to also address supplemental off-chip control storage and to use such off-chip supplemental storage in substitution for portions of the on-chip storage. The processor further includes simplified arithmetic and logic (ALU) circuitry wherein the adder circuit has portions selectively gated to perform other functions with a reduced logic circuit requirement. Processor function is also enhanced by providing a read only storage (ROS) array in association with the ALU to provide multiple register loading and control functions in response to certain addresses. The processor also includes memory control circuitry that permits a group of like processors to access a single, external memory on a dynamic, prioritized basis.

Abstract: In a control unit having a read only memory, a control program is provided which has provision for all features with which the machine may be equipped and for a selected number of future features. The control program contains one or more mainline control loops which interrogate mainline and feature functions sequentially to determine whether a function requires service. If a function is present and requires service, the appropriate routine is executed whereafter the mainline control program proceeds to execute the next indicated control program instruction. If a function is present, but does not require service, a normal return or other procedure is executed to return to the control loop. When a feature is addressed which is not present, a feature return is executed forcing the control program back to the instruction following the last branch.