Patents by Inventor Larry Louis Moresco
Larry Louis Moresco has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6733685Abstract: Methods of planarizing structures formed on the surfaces of substrates and wafers are disclosed. The methods form a planarizing layer over the surface and the structures, or the locations where the structures are to be formed, such that the top surface of the layer has low areas between the locations of the structures, and such that the low areas lie substantially within a plane which is below the tops of the structures. A polish-stop layer is thee formed over the low areas of the planarizing layer, the polish-stop layer being more resistant to polishing than the planarizing layer and, preferably, the structures. The resulting surface is then polished. The polishing may be accomplished by, for example, standard mechanical polishing, and chemical-mechanical polishing.Type: GrantFiled: June 12, 2001Date of Patent: May 11, 2004Assignee: Fujitsu LimitedInventors: Solomon I. Beilin, Michael G. Lee, William T. Chou, Larry Louis Moresco, Wen-chou Vincent Wang
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Publication number: 20010042734Abstract: Methods of planarizing structures formed on the surfaces of substrates and wafers are disclosed. The methods form a planarizing layer over the surface and the structures, or the locations where the structures are to be formed, such that the top surface of the layer has low areas between the locations of the structures, and such that the low areas lie substantially within a plane which is below the tops of the structures. A polish-stop layer is thee formed over the low areas of the planarizing layer, the polish-stop layer being more resistant to polishing than the planarizing layer and, preferably, the structures. The resulting surface is then polished. The polishing may be accomplished by, for example, standard mechanical polishing, and chemical-mechanical polishing.Type: ApplicationFiled: June 12, 2001Publication date: November 22, 2001Inventors: Solomon I. Beilin, Michael G. Lee, William T. Chou, Larry Louis Moresco, Wen-Chou Vincent Wang
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Patent number: 6034332Abstract: A power distribution structure for a multichip module including, a base plate, a plurality of mesas arranged in a pattern are formed on the base plate, the mesas having electrically conductive upper surfaces which lie substantially in a single plane. A thin, conformal dielectric layer is formed over the exposed side surfaces of the mesas and the exposed surfaces of the support base and a conductive material is deposited over the dielectric material filling the area between and surrounding the mesas. The upper surfaces of the mesas and the upper surface of the conductive material surrounding the mesas lie in substantially one plane and are electrically isolated from each other by the dielectric material.Type: GrantFiled: March 11, 1998Date of Patent: March 7, 2000Assignee: Fujitsu LimitedInventors: Larry Louis Moresco, Richard L. Wheeler, Solomon I. Beilin, David A. Horine
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Patent number: 5930890Abstract: An interconnecting post for mounting a microelectronic device such as an integral circuit chip is fabricated with generally uniform cross-section, by forming a first layer of positive photoresist on a substrate, soft-baking that first layer and exposing it for a short time with a wide-apertured mask or simply a UV blank flood exposure. Without developing the first layer, a second layer of positive resist is then applied over the first layer, soft-baked, and then exposed with a narrow-apertured mask. During the soft-baking of the second layer, some of its activator in the photoresist compound diffuses into the exposed portion of the first layer and modifies its solubility in such a way that, when the layers are subsequently developed, the developer partially undercuts the unexposed portion of the first layer to form in the photoresist an opening of generally uniform cross-section. This opening can then be filled by plating to produce a strong, integral interconnect post.Type: GrantFiled: April 21, 1997Date of Patent: August 3, 1999Assignee: Fujitsu LimitedInventors: William T. Chou, Solomon I. Beilin, David A. Horine, David Kudzuma, Michael G. Lee, Larry Louis Moresco, Wen-chou Vincent Wang
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Patent number: 5916453Abstract: Methods of planarizing structures formed on the surfaces of substrates and wafers are disclosed. The methods form a planarizing layer over the surface and the structures, or the locations where the structures are to be formed, such that the top surface of the layer has low areas between the locations of the structures, and such that the low areas lie substantially within a plane which is below the tops of the structures. A polish-stop layer is then formed over the low areas of the planarizing layer, the polish-stop layer being more resistant to polishing than the planarizing layer and, preferably, the structures. The resulting surface is then polished. The polishing may be accomplished by, for example, standard mechanical polishing, and chemical-mechanical polishing.Type: GrantFiled: September 20, 1996Date of Patent: June 29, 1999Assignee: Fujitsu LimitedInventors: Solomon I. Beilin, Michael G. Lee, William T. Chou, Larry Louis Moresco, Wen-chou Vincent Wang
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Patent number: 5773889Abstract: An interconnect structure for connecting an integrated circuit (IC) chip to a supporting substrate is described. The supporting substrate serves to communicate signals between the IC chip and the "outside world," such as other IC chips. In one embodiment, the interconnect structure comprises an interconnect substrate having a first post disposed on one of its surfaces and a second post disposed on another of its surfaces. One post is for contacting the IC chip and the other is for contacting the major substrate. Each post comprising an elongated body having top and bottom ends, with the bottom end being mounted to one of the substrate surfaces and the top end having a substantially flat surface which is substantially co-planer with the substrate surface. The interconnect substrate further comprises a means for de-concentrating the mechanical stain present at one or both of the top and bottom ends of each post.Type: GrantFiled: September 23, 1996Date of Patent: June 30, 1998Assignee: Fujitsu LimitedInventors: David George Love, Larry Louis Moresco, William Tai-Hua Chou, David Albert Horine, Connie Mak Wong, Solomon Isaac Beilin
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Patent number: 5765279Abstract: A power distribution structure for a multichip module and a method for fabricating the same are shown. According to the method of the present invention, a base plate is provided, a plurality of mesas arranged in a pattern are formed on the base plate, the mesas having electrically conductive upper surfaces which lie substantially in a single plane. A thin, conformal dielectric layer is then formed over the exposed surfaces of the mesas and the support base and a conductive material is deposited over the dielectric material filling the area between and surrounding the mesas. The resulting structure is then planarized, as by polishing, such that the upper surfaces of the mesas and the upper surface of the conductive material surrounding the mesas lie in substantially one plane and are electrically isolated from each other by the dielectric material.Type: GrantFiled: May 22, 1995Date of Patent: June 16, 1998Assignee: Fujitsu LimitedInventors: Larry Louis Moresco, Richard L. Wheeler, Solomon I. Beilin, David A. Horine
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Patent number: 5722162Abstract: An interconnecting post for mounting a microelectronic device such as an integral circuit chip is fabricated with generally uniform cross-section, by forming a first layer of positive photoresist on a substrate, soft-baking that first layer and exposing it for a short time with a wide-apertured mask or simply a UV blank flood exposure. Without developing the first layer, a second layer of positive resist is then applied over the first layer, soft-baked, and then exposed with a narrow-apertured mask. During the soft-baking of the second layer, some of its activator in the photoresist compound diffuses into the exposed portion of the first layer and modifies its solubility in such a way that, when the layers are subsequently developed, the developer partially undercuts the unexposed portion of the first layer to form in the photoresist an opening of generally uniform cross-section. This opening can then be filled by plating to produce a strong, integral interconnect post.Type: GrantFiled: October 12, 1995Date of Patent: March 3, 1998Assignee: Fujitsu LimitedInventors: William T. Chou, Solomon I. Beilin, David A. Horine, David Kudzuma, Michael G. Lee, Larry Louis Moresco, Wen-chou Vincent Wang