Patents by Inventor Larry M. DeVito

Larry M. DeVito has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Circuit construction for controlling saturation of a transistor
    Patent number: 5545918
    Abstract: An integrated circuit including a semiconductor substrate, a semiconductor layer formed on the substrate, a desired bipolar transistor formed in the semiconductor layer. First and second parasitic elements are formed in the integrated circuit. An element is provided which detects when the second parasitic element becomes active or which prevents increase of the collector-to-emitter voltage of the desired bipolar transistor in response to current flowing through the second parasitic transistor. This element may be a semiconductor region formed in the semiconductor layer. The transistor may be an npn or pnp type transistor manufactured according to a complementary bipolar process or other process which results in a transistor with first and second parasitic elements. The present invention is also well-suited for use in the output stage of an operational amplifier.
    Type: Grant
    Filed: March 15, 1995
    Date of Patent: August 13, 1996
    Assignee: Analog Devices, Inc.
    Inventors: Francisco Dos Santos, Jr., Larry M. DeVito
  • Circuit construction for controlling saturation of a transistor
    Patent number: 5418386
    Abstract: An integrated circuit including a semiconductor substrate, a semiconductor layer formed on the substrate, a desired bipolar transistor formed in the semiconductor layer. First and second parasitic elements are formed in the integrated circuit. An element is provided which detects when the second parasitic element becomes active or which prevents increase of the collector-to-emitter voltage of the desired bipolar transistor in response to current flowing through the second parasitic transistor. This element may be a semiconductor region formed in the semiconductor layer. The transistor may be an npn or pnp type transistor manufactured according to a complementary bipolar process or other process which results in a transistor with first and second parasitic elements. The present invention is also well-suited for use in the output stage of an operational amplifier.
    Type: Grant
    Filed: July 25, 1994
    Date of Patent: May 23, 1995
    Assignee: Analog Devices, Inc.
    Inventors: Francisco Dos Santos, Jr., Larry M. DeVito