Abstract: A computing device having partitions, and a method of communicating between partitions, are disclosed wherein at least one partition comprises: at least one register substantially always accessible to other partitions and capable of defining an address area; at least one address area that may be accessible to other partitions and is capable of being defined by the at least one register; and address areas other than the at least one accessible address area that are not accessible to other partitions. A method of processing interrupts comprising receiving an interrupt, assessing the origin of the interrupt, accepting, rejecting, or further assessing the interrupt, depending on its origin, when further assessing the interrupt, accepting or rejecting the interrupt depending on its contents, and forwarding accepted interrupts but not rejected interrupts to a target processor, and a device carrying out that method are also disclosed.

Abstract: The disclosed embodiments relate to a security module and a method of operating a security module. The method may comprise the acts of detecting a second security module, determining whether a key associated with the second security module is available to the first security module, and obtaining the key associated with the second security module if the key associated with the second security module is not available to the first security module. The security module may comprise a detector that is adapted to detect another security module and determine whether one of a plurality of keys is associated with the other security module, and a device that obtains at least one key associated with the other security module if the one of the plurality of keys is not associated with the other security module.

Abstract: A computing device having partitions, and a method of communicating between partitions, are disclosed wherein each partition comprises at least one address area readable but not writable from the other of the at least two partitions. In one embodiment one partition sends to the other partition a request for information, which information is in the other partition in an address area not accessible to the one partition, the other partition copies the information to an address area accessible to the one partition, and the one partition reads the information from the accessible address area. In another embodiment the at least one accessible address area of each partition includes a data area and a consumer pointer indicating the position to which that partition has read the data area in another partition.

Abstract: Information objects and system firmware for a processor in a partitionable computing system are disclosed. One object comprises information corresponding to components of the computer system. The information comprises entries defining an address and a size for registers normally accessible to other partitions. The registers are capable of defining an address area such that in use the processor is arranged to permit other partitions to access at least one address area defined by the at least one register and to deny other partitions access to address areas other than the at least one accessible address area.

Abstract: A method and apparatus for initializing multiple security modules are provided. The method may comprise the acts of determining if the security module is a controlling security module or a subordinate security module, generating at least one key if the security module is the controlling security module, and receiving at least one key from another security module if the security module is the subordinate security module. The apparatus may comprise a detector that is adapted to determine if the security module is a controlling security module or a subordinate security module, a key generator that generates a key for the security module if the security module is the controlling security module, and a key receiver that receives a key from another security module if the security module is the subordinate security module.

Abstract: The present invention, in various embodiments, provides techniques for allocating resources for efficient use by a program. In one embodiment, a method implementing the techniques comprises the steps of identifying an I/O device connected to a storage device storing data associated with the program, and allocating memory arrays and a processor both of which having a shortest distance to the I/O device. In one embodiment, the resources reside in a plurality of nodes each of which includes one or a combination one or more of an I/O device, memory arrays, and a processor. Further, the resources are grouped in a node if they are on the same system bus or if they are connected to a chip providing point-to-point links to resources. In one embodiment, the relative distance between the resources is stored in a table embedded in firmware portable from one operating system to another operating system.

Abstract: The present invention, in various embodiments, provides techniques for allocating resources for efficient use by a program. In one embodiment, a method implementing the techniques comprises the steps of identifying an I/O device connected to a storage device storing data associated with the program, and allocating memory arrays and a processor both of which having a shortest distance to the I/O device. In one embodiment, the resources reside in a plurality of nodes each of which includes one or a combination one or more of an I/O device, memory arrays, and a processor. Further, the resources are grouped in a node if they are on the same system bus or if they are connected to a chip providing point-to-point links to resources. In one embodiment, the relative distance between the resources is stored in a table embedded in firmware portable from one operating system to another operating system.

Abstract: A split transaction bus system that accommodates atomic operations without locking the bus and without the possibility of deadlock during the atomic operations. The bus system may be used in a computer system that includes a bus, component modules that send transactions to each other on the bus, and a bus controller that limits the types of transactions that can be sent on the bus at any given time. When one module is performing an atomic operation, the bus controller limits transactions to those that do not change the memory image that existed when the atomic operation was commenced. The bus controller, however, permits responses or returns of data, assuming the response or return does not alter the current value of data.