Patents by Inventor Larry Phillips

Larry Phillips has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5623311
    Abstract: A decoder for a video signal encoded according to the MPEG-2 standard includes a single high-bandwidth memory and a digital phase-locked loop. This memory has a single memory port. The memory is used to hold 1) the input bit-stream, 2) first and second reference frames used for motion compensated processing, and 3) image data representing a field that is currently being decoded. The decoder includes circuitry which stores and fetches the bit-stream data, fetches the reference frame data, stores the image data for the field that is currently being decoded in block format and fetches this image data for conversion to raster-scan format. All of these memory access operations are time division multiplexed and use the single memory port. The digital phase locked loop (DPLL) counts pulses of a 27 MHz system clock signal, defined in the MPEG-2 standard, to generate a count value.
    Type: Grant
    Filed: October 28, 1994
    Date of Patent: April 22, 1997
    Assignee: Matsushita Electric Corporation of America
    Inventors: Larry Phillips, Shuji Inoue, Edwin R. Meyer
  • Patent number: 5510842
    Abstract: A parallel decoder for an MPEG-2 encoded video signal includes a deformatter which separates the input bit stream into multiple portions, each representing a respectively different section of the HDTV image. The separate portions are processed in parallel by respective decoders. In order to perform motion compensated processing, each of the four decoders includes a memory that holds data representing the entire image. Each decoder provides its decoded output data to all of the decoders to maintain the data in the respective memories.
    Type: Grant
    Filed: May 4, 1994
    Date of Patent: April 23, 1996
    Assignee: Matsushita Electric Corporation of America
    Inventors: Larry Phillips, Saiprasad V. Naimpally, Robert Meyer, Shuji Inoue
  • Patent number: 5485215
    Abstract: A system and method for filtering a digital signal having a relatively high data rate uses circuitry which operates at a lower data rate. The filter includes an input section which receives the input signal and which divides the input signal into a plurality of contiguous segments. The system also includes a first filter which receives samples representing one of the plurality of segments and adjacent samples from the next contiguous one of the segments and which filters all of the received samples to produce a first filtered signal. A second filter receives samples of the next contiguous segment and filters those samples to produce a second filtered signal. The filtered signals are combined by providing the samples of the second filtered signal immediately after the samples of the first filtered signal to produce a filtered output signal.
    Type: Grant
    Filed: May 19, 1994
    Date of Patent: January 16, 1996
    Assignee: Matsushita Electric Corporation of America
    Inventors: Edwin R. Meyer, Saiprasad V. Naimpally, Larry Phillips, Shuji Inoue