Abstract: Exemplary embodiments provide high-quality layered semiconductor devices and methods for their fabrication. The high-quality layered semiconductor device can be formed in planar with low defect densities and with strain relieved through a plurality of arrays of misfit dislocations formed at the interface of highly lattice-mismatched layers of the device. The high-quality layered semiconductor device can be formed using various materials systems and can be incorporated into various opto-electronic and electronic devices. In an exemplary embodiment, an emitter device can include monolithic quantum well (QW) lasers directly disposed on a SOI or silicon substrate for waveguide coupled integration. In another exemplary embodiment, a superlattice (SL) photodetector and its focal plane array can include a III-Sb active region formed over a large GaAs substrate using SLS technologies.

Abstract: Exemplary embodiments provide a semiconductor fabrication method including a combination of monolithic integration techniques with wafer bonding techniques. The resulting semiconductor devices can be used in a wide variety of opto-electronic and/or electronic applications such as lasers, light emitting diodes (LEDs), phototvoltaics, photodetectors and transistors. In an exemplary embodiment, the semiconductor device can be formed by first forming an active-device structure including an active-device section disposed on a thinned III-V substrate. The active-device section can include OP and/or EP VCSEL devices. A high-quality monolithic integration structure can then be formed with low defect density through an interfacial misfit dislocation. In the high-quality monolithic integration structure, a thinned III-V mating layer can be formed over a silicon substrate.

Abstract: Exemplary embodiments provide high-quality layered semiconductor devices and methods for their fabrication. The high-quality layered semiconductor device can be formed in planar with low defect densities and with strain relieved through a plurality of arrays of misfit dislocations formed at the interface of highly lattice-mismatched layers of the device. The high-quality layered semiconductor device can be formed using various materials systems and can be incorporated into various opto-electronic and electronic devices. In an exemplary embodiment, an emitter device can include monolithic quantum well (QW) lasers directly disposed on a SOI or silicon substrate for waveguide coupled integration. In another exemplary embodiment, a superlattice (SL) photodetector and its focal plane array can include a III-Sb active region formed over a large GaAs substrate using SLS technologies.

Abstract: A semiconductor device is supported by a substrate with a smaller lattice constant. A metamorphic buffer provides a transition from the smaller lattice constant of the substrate to the larger lattice constant of the semiconductor device. In one application, the semiconductor device has a lattice constant of between approximately 6.1 and 6.35 angstroms, metamorphic buffer layers include Sb (e.g., AlInSb buffer layers), and the substrate has a smaller lattice constant (e.g., Si, InP or GaAs substrates).

Abstract: Structures and methods for electronic devices with improved conductive regions are provided. The conductive region may include digital alloy superlattice structures, which allow higher doping levels to be achieved than for a bulk (random) alloy with the same average composition. Furthermore, the superlattice structures may improve the resistivity of the region, improving the current spreading of the region and hence the electronic properties of electronic devices such as optoelectronic devices.

Abstract: Lattice mismatched epitaxy and methods for lattice mismatched epitaxy are provided. The method includes providing a growth substrate and forming a plurality of quantum dots, such as, for example, AlSb quantum dots, on the growth substrate. The method further includes forming a crystallographic nucleation layer by growth and coalescence of the plurality of quantum dots, wherein the nucleation layer is essentially free from vertically propagating defects. The method using quantum dots can be used to overcome the restraints of critical thickness in lattice mismatched epitaxy to allow effective integration of various existing substrate technologies with device technologies.

Abstract: Lattice mismatched epitaxy and methods for lattice mismatched epitaxy are provided. The method includes providing a growth substrate and forming a plurality of quantum dots, such as, for example, AlSb quantum dots, on the growth substrate. The method further includes forming a crystallographic nucleation layer by growth and coalescence of the plurality of quantum dots, wherein the nucleation layer is essentially free from vertically propagating defects. The method using quantum dots can be used to overcome the restraints of critical thickness in lattice mismatched epitaxy to allow effective integration of various existing substrate technologies with device technologies.

Abstract: A symmetric double heterojunction transistor consisting of a lightly doped wide bandgap--heavily doped narrow bandgap--lightly doped wide bandgap structure with the wide bandgap materials having a conductivity type opposite to that of the narrow bandgap material is optically accessed, symmetric with respect to the polarity of applied bias across the transistor and has linear current-voltage characteristics through the origin. A preferred embodiment uses a nGa.sub.1-x Al.sub.x As-pGaAs-nGa.sub.1-x Al.sub.x As structure.