Abstract: A system and method for coordinating control setting with respect to an automated input/output (I/O) processor. A state machine having a transition algorithm can be configured in association with a storage controller in order to permit multiple entities to safely transmit an I/O request to an I/O device. Specific combinations of control bits associated with a fast path engine can be determined by identifying different modes with respect to the behavior of the fast path engine. Each mode can be assigned as a state with respect to the state machine. An I/O path exception and error condition that can cause transitions between the states can be determined and the transitions can be assigned from one state to another state. A generic logic template can then be configured to govern the transitions with respect to the state machine. The logic can be executed when an event occurs in order to trigger multiple state transition and/or modifications with respect to the hardware control bits of the fast path engine.

Abstract: A system and method for coordinating control setting with respect to an automated input/output (I/O) processor. A state machine having a transition algorithm can be configured in association with a storage controller in order to permit multiple entities to safely transmit an I/O request to an I/O device. Specific combinations of control bits associated with a fast path engine can be determined by identifying different modes with respect to the behavior of the fast path engine. Each mode can be assigned as a state with respect to the state machine. An I/O path exception and error condition that can cause transitions between the states can be determined and the transitions can be assigned from one state to another state. A generic logic template can then be configured to govern the transitions with respect to the state machine. The logic can be executed when an event occurs in order to trigger multiple state transition and/or modifications with respect to the hardware control bits of the fast path engine.

Abstract: Methods and systems use a hardware controller for controlling commands sent to a plurality of target devices. The controller controls queuing of commands according to respective target device allowed queue depths set in hardware circuitry of the controller. Status of each one of the plurality of target devices is monitored also using controller hardware circuitry. The allowed queue depths can be set in the hardware controller circuitry using firmware and can by dynamically adjustable based on the status of the target devices. Hardware circuitry of the controller is also used to control queuing of commands, for each one of the plurality of target devices, according to the queue depth setting for the target device.