Abstract: A dedicated context cycling microprocessor which features a plurality of input/output circuits for receiving and transmitting information and an individual set of dedicated on-board resources for each plurality of processing contexts. A distinct processing context is provided for each of a plurality of the input/output circuits, and a timed context is also provided for concurrently scheduling multiple processing contexts and enforcing time constraints associated with this schedule. The timed context has a pseudo-queue list which represents an ordered set of data parameters and program memory addresses for scheduling each of the processing contexts. The dedicated on-board resources include a plurality of registers for each of the processing contexts, such as at least one general purpose register and a program counter. A multiplexer circuit is also provided for moving data between the input/output circuits, the dedicated registers of the processing contexts and the computational unit.