Abstract: Semiconductor devices comprising a getter material are described. The getter material can be located in or over the active region of the device and/or in or over a termination region of the device. The getter material can be a conductive or an insulating material. The getter material can be present as a continuous or discontinuous film. The device can be a SiC semiconductor device such as a SiC vertical MOSFET. Methods of making the devices are also described.

Abstract: Semiconductor devices comprising a getter material are described. The getter material can be located in or over the active region of the device and/or in or over a termination region of the device. The getter material can be a conductive or an insulating material. The getter material can be present as a continuous or discontinuous film. The device can be a SiC semiconductor device such as a SiC vertical MOSFET. Methods of making the devices are also described.

Abstract: Semiconductor devices comprising a getter material are described. The getter material can be located in or over the active region of the device and/or in or over a termination region of the device. The getter material can be a conductive or an insulating material. The getter material can be present as a continuous or discontinuous film. The device can be a SiC semiconductor device such as a SiC vertical MOSFET. Methods of making the devices are also described.

Abstract: Semiconductor devices comprising a getter material are described. The getter material can be located in or over the active region of the device and/or in or over a termination region of the device. The getter material can be a conductive or an insulating material. The getter material can be present as a continuous or discontinuous film. The device can be a SiC semiconductor device such as a SiC vertical MOSFET. Methods of making the devices are also described.

Abstract: A silicon carbide metal semiconductor field-effect transistor includes a bi-layer silicon carbide buffer for improving electron confinement in the channel region and/or a layer disposed over at least the channel region of the transistor for suppressing surface effects caused by dangling bonds and interface states. Also, a sloped MESA fabrication method which utilizes a dielectric etch mask that protects the MESA top surface during MESA processing and enables formation of sloped MESA sidewalls.

Abstract: A crystalline composition is provided that includes gallium and nitrogen. The crystalline composition may have an amount of oxygen present in a concentration of less than about 3×1018 per cubic centimeter, and may be free of two-dimensional planar boundary defects in a determined volume of the crystalline composition. The volume may have at least one dimension that is about 2.75 millimeters or greater, and the volume may have a one-dimensional linear defect dislocation density of less than about 10,000 per square centimeter.

Abstract: A crystalline composition is provided. The crystalline composition may include gallium and nitrogen; and the crystalline composition may have an infrared absorption peak at about 3175 cm?1, with an absorbance per unit thickness of greater than about 0.01 cm?1.

Abstract: A semiconductor material having an epitaxial layer formed thereon and methods of forming an epitaxial layer on a semiconductor material are provided. The method includes disposing a masking layer and patterning the masking layer to form openings and growing an epitaxial layer through the openings and over the masking layer where the epitaxial layer is coalescent.

Abstract: A crystal comprising gallium nitride is disclosed. The crystal has at least one grain having at least one dimension greater than 2.75 mm, a dislocation density less than about 104 cm?2, and is substantially free of tilt boundaries.

Abstract: A crystalline composition is provided that includes gallium and nitrogen. The crystalline composition may have an amount of oxygen present in a concentration of less than about 3×1018 per cubic centimeter, and may be free of two-dimensional planar boundary defects in a determined volume of the crystalline composition. The volume may have at least one dimension that is about 2.75 millimeters or greater, and the volume may have a one-dimensional linear defect dislocation density of less than about 10,000 per square centimeter.

Abstract: A method of processing a semiconductor substrate is provided. The method includes depositing an amorphous hydrogenated carbon film on a semiconductor substrate using a low temperature plasma deposition process and performing at least one high temperature processing step on the semiconductor substrate. The SiC substrate is processed by ion implanting at least one dopant species into at least one selected region of the SiC substrate, depositing a amorphous hydrogenated carbon film on the SiC substrate using a plasma enhanced chemical vapor deposition (PECVD) process, performing at least one high temperature processing step on the SiC substrate and removing the amorphous hydrogenated carbon film after performing the high temperature processing step.

Abstract: A composite structure having a silicon carbide epitaxial layer is provided. The epitaxial layer includes at least four regions arranged vertically and defining respective interfaces, where each of the regions is characterized by a respective impurity concentration, where the impurity concentrations vary across each of the interfaces, and where each of the impurity concentrations exceeds 1×107 cm?3 for at least one single impurity in all of the regions.

Abstract: A power device includes at least one n-type semiconductor layer and at least one p-type silicon carbide epitaxial layer comprising gallium acceptors. Another power device includes at least one epitaxial silicon carbide layer and at least one p-type region formed epitaxially in the epitaxial silicon carbide layer. The p-type region comprises gallium acceptors. A method for forming a semiconductor device includes forming a first conductivity type semiconductor layer on a substrate, forming a second conductivity type semiconductor layer on the first conductivity type semiconductor layer. At least one of the semiconductor layers comprises silicon carbide, and one of the forming steps comprises epitaxially doping the respective silicon carbide layer with gallium acceptors.

Abstract: There is provided a GaN single crystal at least about 2 millimeters in diameter, with a dislocation density less than about 104 cm?1, and having no tilt boundaries. A method of forming a GaN single crystal is also disclosed. The method includes providing a nucleation center, a GaN source material, and a GaN solvent in a chamber. The chamber is pressurized. First and second temperature distributions are generated in the chamber such that the solvent is supersaturated in the nucleation region of the chamber. The first and second temperature distributions have different temperature gradients within the chamber.

Abstract: A crystalline composition is provided. The crystalline composition may include gallium and nitrogen; and the crystalline composition may have an infrared absorption peak at about 3175 cm?1, with an absorbance per unit thickness of greater than about 0.01 cm?1.

Abstract: A method for removing defects at high pressure and high temperature (HP/HT) or for relieving strain in a non-diamond crystal commences by providing a crystal, which contains defects, and a pressure medium. The crystal and the pressure medium are disposed in a high pressure cell and placed in a high pressure apparatus, for processing under reaction conditions of sufficiently high pressure and high temperature for a time adequate for one or more of removing defects or relieving strain in the single crystal.

Abstract: The present invention is directed towards a source of ultraviolet energy, wherein the source is a UV-emitting LED's. In an embodiment of the invention, the UV-LED's are characterized by a base layer material including a substrate, a p-doped semiconductor material, a multiple quantum well, a n-doped semiconductor material, upon which base material a p-type metal resides and wherein the base structure has a mesa configuration, which mesa configuration may be rounded on a boundary surface, or which may be non-rounded, such as a mesa having an upper boundary surface that is flat. In other words, the p-type metal resides upon a mesa formed out of the base structure materials. In a more specific embodiment, the UV-LED structure includes n-type metallization layer, passivation layers, and bond pads positioned at appropriate locations of the device. In a more specific embodiment, the p-type metal layer is encapsulated in the encapsulating layer.

Abstract: A silicon carbide metal semiconductor field-effect transistor includes a bi-layer silicon carbide buffer for improving electron confinement in the channel region and/or a layer disposed over at least the channel region of the transistor for suppressing surface effects caused by dangling bonds and interface states. Also, a sloped MESA fabrication method which utilizes a dielectric etch mask that protects the MESA top surface during MESA processing and enables formation of sloped MESA sidewalls.

Abstract: A GaN crystal having up to about 5 mole percent of at least one of aluminum, indium, and combinations thereof. The GaN crystal has at least one grain having a diameter greater than 2 mm, a dislocation density less than about 104 cm?2, and is substantially free of tilt boundaries.