Patents by Inventor Larry Rudolph

Larry Rudolph has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170011330
    Abstract: An exemplary system, method and computer accessible medium can be provided that can include generating a digital secure storage area(s) for a user(s), generating, in the secure storage area(s), a module(s) that can include information about the user(s), using a computer-implemented recommender agent(s) to select a receiver(s) to receive the first information and a signal(s) associated with the first information, where receiver(s) can include a verification agent(s), facilitating a verification of the signal(s) by the verification agent, and facilitating the receiver(s) to perform a task(s) based on the verification.
    Type: Application
    Filed: July 11, 2016
    Publication date: January 12, 2017
    Inventors: Bhubaneswar Mishra, Larry Rudolph, Joshua Feuer
  • Publication number: 20130080709
    Abstract: A processor may operate in one of a plurality of operating states. In a Normal operating state, the processor is not involved with a memory transaction. Upon receipt of a transaction instruction to access a memory location, the processor transitions to a Transaction operating state. In the Transaction operating state, the processor performs changes to a cache line and data associated with the memory location. While in the Transaction operating state, any changes to the data and the cache line are not visible to other processors in the computing system. These changes become visible upon the processor entering a Commit operating state in response to receipt of a commit instruction. After changes become visible, the processor returns to the Normal operating state. If an abort event occurs prior to receipt of the commit instruction, the processor transitions to an Abort operating state where any changes to the data and cache line are discarded.
    Type: Application
    Filed: November 21, 2012
    Publication date: March 28, 2013
    Inventors: Steven C. Miller, Martin M. Deneroff, Curt F. Schimmel, Larry Rudolph, Charles E. Leiserson, Bradley C. Kuszmaul, Krste Asanovic
  • Publication number: 20130066951
    Abstract: A communication system is presented for managing data transfer via a communication network. The communication system comprises a server system connected to a plurality of client systems via a first management network of said communication network. Such first management network may for example be operable as multi-hops network. The server system is configured and operable to be responsive to data pieces from the client systems via said first management network, to selectively switch between first and second modes of operation. In the first operational mode, the server system manages and executes data transfer to and from the client systems through the first management network. In the second operational mode, the server system operates to manage direct data transfer between the client systems via a second data network of said communication network connecting the client systems between them. The second data network may for example be operable as ad-hoc circuits.
    Type: Application
    Filed: November 18, 2010
    Publication date: March 14, 2013
    Applicant: YISSUM RESEARCH DEVELOPMENT COMPANY OF THE HEBREW UNIVERSITY OF JERUSALEM
    Inventors: Aharon Agranat, Larry Rudolph, Noam Sapiens
  • Patent number: 8321634
    Abstract: A processor may operate in one of a plurality of operating states. In a Normal operating state, the processor is not involved with a memory transaction. Upon receipt of a transaction instruction to access a memory location, the processor transitions to a Transaction operating state. In the Transaction operating state, the processor performs changes to a cache line and data associated with the memory location. While in the Transaction operating state, any changes to the data and the cache line is not visible to other processors in the computing system. These changes become visible upon the processor entering a Commit operating state in response to receipt of a commit instruction. After changes become visible, the processor returns to the Normal operating state. If an abort event occurs prior to receipt of the commit instruction, the processor transitions to an Abort operating state where any changes to the data and cache line are discarded.
    Type: Grant
    Filed: April 11, 2011
    Date of Patent: November 27, 2012
    Assignee: Silicon Graphics International Corp.
    Inventors: Steven C. Miller, Martin M. Deneroff, Curt F. Schimmel, Larry Rudolph, Charles E. Leiserson, Bradley C. Kuszmaul, Krste Asanovic
  • Publication number: 20110191545
    Abstract: A processor may operate in one of a plurality of operating states. In a Normal operating state, the processor is not involved with a memory transaction. Upon receipt of a transaction instruction to access a memory location, the processor transitions to a Transaction operating state. In the Transaction operating state, the processor performs changes to a cache line and data associated with the memory location. While in the Transaction operating state, any changes to the data and the cache line is not visible to other processors in the computing system. These changes become visible upon the processor entering a Commit operating state in response to receipt of a commit instruction. After changes become visible, the processor returns to the Normal operating state. If an abort event occurs prior to receipt of the commit instruction, the processor transitions to an Abort operating state where any changes to the data and cache line are discarded.
    Type: Application
    Filed: April 11, 2011
    Publication date: August 4, 2011
    Inventors: Steven C. Miller, Martin M. Deneroff, Curt F. Schimmel, Larry Rudolph, Charles E. Leiserson, Bradley C. Kuszmaul, Krste Asanovic
  • Patent number: 7925839
    Abstract: A processor may operate in one of a plurality of operating states. In a Normal operating state, the processor is not involved with a memory transaction. Upon receipt of a transaction instruction to access a memory location, the processor transitions to a Transaction operating state. In the Transaction operating state, the processor performs changes to a cache line and data associated with the memory location. While in the Transaction operating state, any changes to the data and the cache line is not visible to other processors in the computing system. These changes become visible upon the processor entering a Commit operating state in response to receipt of a commit instruction. After changes become visible, the processor returns to the Normal operating state. If an abort event occurs prior to receipt of the commit instruction, the processor transitions to an Abort operating state where any changes to the data and cache line are discarded.
    Type: Grant
    Filed: July 7, 2008
    Date of Patent: April 12, 2011
    Assignee: Silicon Graphics International
    Inventors: Steven C. Miller, Martin M. Deneroff, Curt F. Schimmel, Larry Rudolph, Charles E. Leiserson, Bradley C. Kuszmaul, Krste Asanovic
  • Patent number: 7398359
    Abstract: A processor may operate in one of a plurality of operating states. In a Normal operating state, the processor is not involved with a memory transaction. Upon receipt of a transaction instruction to access a memory location, the processor transitions to a Transaction operating state. In the Transaction operating state, the processor performs changes to a cache line and data associated with the memory location. While in the Transaction operating state, any changes to the data and the cache line is not visible to other processors in the computing system. These changes become visible upon the processor entering a Commit operating state in response to receipt of a commit instruction. After changes become visible, the processor returns to the Normal operating state. If an abort event occurs prior to receipt of the commit instruction, the processor transitions to an Abort operating state where any changes to the data and cache line are discarded.
    Type: Grant
    Filed: April 30, 2004
    Date of Patent: July 8, 2008
    Assignee: Silicon Graphics, Inc.
    Inventors: Steven C. Miller, Martin M. Deneroff, Curt F. Schimmel, Larry Rudolph, Charles E. Leiserson, Bradley C. Kuszmaul, Krste Asanovic
  • Patent number: 6542264
    Abstract: The present invention relates to an optical switch comprising a paraelectric photorefractive material, storing a hologram, possibly a latent hologram, whose reconstruction, or activation and reconstruction, is controllable by means of an applied electric field. The hologram may be formed by spatial modulation of the refractive index of the paraelectric photorefractive material, which arises from the quadratic electro-optic effect induced by the combined action of a spatially modulated space charge within the paraelectric photorefractive material and an external applied electric field. The present invention further relates to a switching network, such as a multistage network, for use in an optical communications system, incorporating at least one optical switch according to the invention.
    Type: Grant
    Filed: July 6, 1999
    Date of Patent: April 1, 2003
    Assignee: Yissum Research Development Company of the Hebrew University of Jerusalem
    Inventors: Aharon J. Agranat, Benny Pessach, Larry Rudolph Rogel
  • Patent number: 6063751
    Abstract: A process for preparing a low density detergent composition is disclosed. The process includes the steps of agglomerating a detergent surfactant paste and dry starting detergent material in a high speed mixer to obtain detergent agglomerates wherein the detergent agglomerates include at least 3% by weight water and dielectrically heating the detergent agglomerates so as to form the detergent composition having a density of below 600 g/l.
    Type: Grant
    Filed: April 5, 1999
    Date of Patent: May 16, 2000
    Assignee: The Procter & Gamble Company
    Inventors: Paul Amaat France, Larry Rudolph Genskow, Wayne Edward Beimesch
  • Patent number: 5887090
    Abstract: An optical interconnection network in which more than one communication can ccur at any give time is disclosed. The interconnection network can form part of a parallel computer, a fiber optic switching network, a massive video or data server or an asynchronous transfer mode (ATM) network. The network includes transmission network elements, reception network elements and a holographic storage element. The holographic storage element is located equidistant form all the transmission and reception network elements and stores therein a multiplicity of holograms. Each volume hologram is responsive to a different angle of incidence of wavelength.
    Type: Grant
    Filed: April 1, 1997
    Date of Patent: March 23, 1999
    Assignee: Yissum Research Development Company of the Hebrew University of Jerusalem
    Inventors: Larry Rudolph, Aharon Agranat
  • Patent number: 5665691
    Abstract: A process for continuously preparing low density detergent agglomerate is provided. The process comprises the steps of: (a) agglomerating a detergent surfactant paste and dry starting detergent material in a high speed mixer to obtain detergent agglomerates, wherein the dry starting detergent material includes a hydrated salt; and (b) drying the detergent agglomerates so as to form the detergent composition having a density of less than about 600 g/l.
    Type: Grant
    Filed: October 4, 1995
    Date of Patent: September 9, 1997
    Assignee: The Procter & Gamble Company
    Inventors: Paul Amatt France, Larry Rudolph Genskow, Wayne Edward Beimesch