Abstract: Novel bioreactor systems, adapted to provide continuous batch incubation of microbes, especially bacteria, are provided. Bioreactor bags are preloaded with inert microbes prior to being shipped to the user. The inert microbes may be substantially dry or in other inert forms, and are stored in soluble containers within the bioreactor bags. Multiple sterile, preloaded, disposable bioreactor bags are used in a self-contained housing. The bags are automatically incubated in the housing and dispensed, preferably into an irrigation system. The system provides serial batch production of useful microbes for a week or more, without further supervision or intervention. Methods of manufacture, methods of use, methods of sales, and methods of farming are also provided.

Abstract: Novel bioreactor systems, adapted to provide continuous batch incubation of microbes, especially bacteria, are provided. Bioreactor bags are preloaded with inert microbes prior to being shipped to the user. The inert microbes may be substantially dry or in other inert forms, and are stored in soluble containers within the bioreactor bags. Multiple sterile, preloaded, disposable bioreactor bags are used in a self-contained housing. The bags are automatically incubated in the housing and dispensed, preferably into an irrigation system. The system provides serial batch production of useful microbes for a week or more, without further supervision or intervention. Methods of manufacture, methods of use, methods of sales, and methods of farming are also provided.

Abstract: Methods and structures and methods of designing structures for charge dissipation in an integrated circuit on an SOI substrate. A first structure includes a charge dissipation ring around a periphery of the integrated circuit chip and one or more charge dissipation pedestals physically and electrically connected to the charge dissipation pedestals. The silicon layer and bulk silicon layer of the SOI substrate are connected by the guard ring and the charge dissipation pedestals. The ground distribution grid of the integrated circuit chip is connected to an uppermost wire segment of one or more charge dissipation pedestals. A second structure, replaces the charge dissipation guard ring with additional charge dissipation pedestal elements.

Abstract: The present invention provides novel bioreactor systems, adapted to provide continuous batch incubation of microbes, especially bacteria. The bioreactor bags are preloaded with dry, inert microbes prior to being shipped to the user. Multiple sterile, preloaded, disposable bioreactor bags are used in a self-contained housing. The bags are automatically incubated in the housing and dispensed, preferably into an irrigation system. The system will provide serial batch production of useful microbes for a week or more, without further supervision or intervention. Methods of manufacture, methods of use, methods of sales, and methods of farming are also provided.

Abstract: Methods and structures and methods of designing structures for charge dissipation in an integrated circuit on an SOI substrate. A first structure includes a charge dissipation ring around a periphery of the integrated circuit chip and one or more charge dissipation pedestals physically and electrically connected to the charge dissipation pedestals. The silicon layer and bulk silicon layer of the SOI substrate are connected by the guard ring and the charge dissipation pedestals. The ground distribution grid of the integrated circuit chip is connected to an uppermost wire segment of one or more charge dissipation pedestals. A second structure, replaces the charge dissipation guard ring with additional charge dissipation pedestal elements.

Abstract: Methods and structures and methods of designing structures for charge dissipation in an integrated circuit on an SOI substrate. A first structure includes a charge dissipation ring around a periphery of the integrated circuit chip and one or more charge dissipation pedestals physically and electrically connected to the charge dissipation pedestals. The silicon layer and bulk silicon layer of the SOI substrate are connected by the guard ring and the charge dissipation pedestals. The ground distribution grid of the integrated circuit chip is connected to an uppermost wire segment of one or more charge dissipation pedestals. A second structure, replaces the charge dissipation guard ring with additional charge dissipation pedestal elements.

Abstract: A system for remotely monitoring the status of one or more fire extinguishers includes means for sensing at least one parameter of each of the fire extinguishers; means for selectively transmitting the sensed parameters along with information identifying the fire extinguishers from which the parameters were sensed; and means for receiving the sensed parameters and identifying information for the fire extinguisher or extinguishers at a common location. Other systems and methods for remotely monitoring the status of multiple fire extinguishers are also provided.

Abstract: A capacitor structure (10) is implemented in an integrated circuit chip (11) along with other devices at the device level in the chip structure. The method of manufacturing the capacitor includes forming an elongated device body (17) on a semiconductor substrate from a first semiconductor material. Fabrication also includes forming lateral regions (20, 22) on both lateral sides of this device body (17). These lateral regions (20, 22) are formed from a second semiconductor material. A dielectric layer (28) is formed over both lateral regions (20, 22) and the device body (17), while an anode layer (30) is formed over the dielectric layer in an area defined by the device body. Each lateral region (20, 22) is coupled to ground at a first end (25) of the elongated device body (17). The anode (30) is coupled to the chip supply voltage at a second end (33) of the device body opposite to the first end. The entire structure is designed and dimensioned to form an area-efficient and high-frequency capacitor.

Abstract: A system for reducing security risks in, for example, an enclosed area where there are documents, computer discs, and other items which may contain security sensitive information. Each security sensitive item has an RFID tag attached thereto, and during non-working hours these items are placed in locked file cabinets, a safe or a vault. The area is periodically interrogated by an RF interrogator to ascertain whether the items are in their locked secured position or are in an open area.

Abstract: A system for remotely monitoring the status of one or more fire extinguishers includes means for sensing at least one parameter of each of the fire extinguishers; means for selectively transmitting the sensed parameters along with information identifying the fire extinguishers from which the parameters were sensed; and means for receiving the sensed parameters and identifying information for the fire extinguisher or extinguishers at a common location. Other systems and methods for remotely monitoring the status of multiple fire extinguishers are also provided.

Abstract: A security system for a building facility where radio frequency tamper-indicating devices are placed in the area of the facility to detect movement and/or relative movement of components under circumstances where such movement may indicate a security risk. One example is where there are ceiling tiles in a false ceiling which may be moved during a covert entry. An RF damage indicating device is placed at juncture locations of the tiles and tendrils of the tamper-indicating devices are positioned so that movement of one of the tiles will break the tendril and cause an alarm signal to be given. In other arrangements, tamper-indicating devices could be attached to security-sensitive objects, containers for the same, and building-related components so that movement of these security-sensitive objects would also trigger an alarm.

Abstract: An EQUATE property is introduced into the layout cell data for a layout design to identify the schematic to which the layout design corresponds. Rather than exploding the layout cell up to the next level for flat checking because the equivalent schematic is not known, the layout cell instances may then be checked hierarchically, with one instance checked internally for compliance with design rules and the like while the remaining instances are merely checked for proper connection to neighboring cells. New layout cell designs may therefore be created as the need arises during layout without requiring schematic checking tools to be rerun.

Abstract: Layout cells having the same name as a corresponding schematic are checked hierarchically, with a single instance of a particular layout cell being checked internally for compliance with design rules and the like while remaining instances are merely checked for proper connection to neighboring cells. Layout cells which are not named the same as any schematic are automatically exploded for flat checking at the transistor level. Thus hierarchical checking is preserved for those layout cell instances named for the corresponding schematic, which should be the large majority of cell instances in any given integrated circuit, while cell instances meeting special layout requirements, which should be a small number of cases, are supported for any given schematic.

Abstract: A system for reducing security risks in, for example, an enclosed area where there are documents, computer discs, and other items which may contain security sensitive information. Each security sensitive item has an RFID tag attached thereto, and during non-working hours these items are placed in locked file cabinets, a safe or a vault. The area is periodically interrogated by an RF interrogator to ascertain whether the items are in their locked secured position or are in an open area.

Abstract: A method and system are disclosed for improving a yield of circuits produced from a semiconductor wafer. A plurality of design rules are established for designing a layout of the circuit within the wafer. A yield-limiting set of the plurality of design rules are selected. Adherence to each of the set of rules throughout all of the layout reduces the yield. For each one of the set of rules, a recommended value is determined. A percentage of occasions each one of the set should be exceeded within the layout is also determined. The layout is then designed so that each one of the set of the plurality of design rules meets or exceeds the recommended value more often than the percentage.

Abstract: The method includes defining at least one sizing parameter for a capacitor arrangement (11). Once the parameter or parameters are defined, the method includes applying at least one sizing parameter to select a particular capacitor arrangement (11) for a free area on the integrated circuit chip (12). The selected capacitor arrangement comprises the largest arrangement which is accommodated within the free area, subject to the sizing parameter or parameters employed. Sizing parameters may include a height dimension range between a maximum and minimum height dimension for the capacitor arrangement, and permissible width dimensions for the capacitor arrangement. Steps in the layout method may be performed on a computer system (51) under the control of operational program code.

Abstract: A system for reducing security risks in, for example, an enclosed area where there are documents, computer discs, and other items which may contain security sensitive information. Each security sensitive item has an RFID tag attached thereto, and during non-working hours these items are placed in locked file cabinets, a safe or a vault. The area is periodically interrogated by an RF interrogator to ascertain whether the items are in their locked secured position or are in an open area.

Abstract: A wafer design layout and method of producing multiple integrated chip types using a single set of masks for a wafer and then at the time the type of chip desired is known, using a few customizing steps to produce the final integrated chip is provided. In one embodiment, the wafer layout includes a plurality of groupings of components and a plurality of dicing channels separating each of the components from others of the components. After the particular type of integrated circuit chip desired is selected, the wafer may then have the final few layers processed and the chips removed using the appropriate dicing channels for the integrated circuit chip desired.

Abstract: A capacitor structure (10) is implemented in an integrated circuit chip (11) along with other devices at the device level in the chip structure. The method of manufacturing the capacitor includes forming an elongated device body (17) on a semiconductor substrate from a first semiconductor material. Fabrication also includes forming lateral regions (20, 22) on both lateral sides of this device body (17). These lateral regions (20, 22) are formed from a second semiconductor material. A dielectric layer (28) is formed over both lateral regions (20, 22) and the device body (17), while an anode layer (30) is formed over the dielectric layer in an area defmed by the device body. Each lateral region (20, 22) is coupled to ground at a first end (25) of the elongated device body (17). The anode (30) is coupled to iff, the chip supply voltage at a second end (33) of the device body opposite to the first end. The entire structure is designed and dimensioned to form an area-efficient and high-frequency capacitor.

Abstract: An alerting device and method to remind personnel of a risk is disclosed. The device has at least two sensors, a logic controller, a power source, and an annunciator that delivers a visual message, with or without an audible alarm, about a risk to a person when the sensors detect the person exiting a predetermined space. In particular, the present invention reminds a person of a security, safety, or health risk upon exiting a predetermined space. More particularly, the present invention reminds a person of an information security risk relating to sensitive, proprietary, confidential, trade secret, classified, or intellectual property information.