Abstract: A barrier gate isolated channel charge coupled device integrated circuit imager which permits the barrier gate to define the transfer channel from an inner shift register to an outer shift register to the exclusion of the field oxide layer. By extending the length of the barrier gate slightly and bringing the storage gate down and out around each barrier gate, and widening the field oxide dimension, relative to one another, the buried channel potential voltage remains high allowing for more efficient charge transfer or, if desired, the isolated channel dimension can be decreased while still maintaining a high minimum buried channel potential voltage.