Abstract: An adder for adding a signal at a first input (A) and a second input (B) to produce an adder output (S) is disclosed. The adder comprises a bypass input (bypass) and a logic circuit, communicatively coupled to the bypass input (bypass), the first input (A), and the second input (B), the logic circuit configured to hold at least one of the first input (A) and the second input (B) according to the bypass input (bypass).

Abstract: An enhanced Booth-encoded adder-array multiplier where the low transition probability partial-products are generated and the adder array has been reorganized to reduce power dissipation when the Booth-encoded input has a large dynamic range. The architecture does not require extra circuits or routing overhead. Power dissipation is reduced by ordering the sequence of partial-product additions such that an increasing sequence of “transition probabilities” is encountered.

Abstract: An enhanced Booth-encoded adder-array multiplier where the low transition probability partial-products are generated and the adder array has been reorganized to reduce power dissipation when the Booth-encoded input has a large dynamic range. The architecture does not require extra circuits or routing overhead. Power dissipation is reduced by ordering the sequence of partial-product additions such that an increasing sequence of “transition probabilities” is encountered.

Abstract: A method, apparatus, article of manufacture, and a memory structure for low power digital processing is disclosed. Tap values are modified by one or more factors to increase computational efficiency and a bias factor used to compensate for changes in the processor output response that result from the modification of the tap values.

Abstract: An adder for adding a signal at a first input (A) and a second input (B) to produce an adder output (S) is disclosed. The adder comprises a bypass input (bypass) and a logic circuit, communicatively coupled to the bypass input (bypass), the first input (A), and the second input (B), the logic circuit configured to hold at least one of the first input (A) and the second input (B) according to the bypass input (bypass).

Abstract: A method, apparatus, article of manufacture, and a memory structure for low power digital processing is disclosed. Tap values are modified by one or more factors to increase computational efficiency and a bias factor used to compensate for changes in the processor output response that result from the modification of the tap values.

Abstract: A method, apparatus, article of manufacture, and a memory structure for low power digital filtering. The method comprises the steps of successively delaying each of the input values {x0,x1, . . . ,xN−1} to create tap values {t0,t1, . . . ,tN−1}, multiplying each of the tap values {t0,t1, . . . ,tN−1} by A•{h0,h1, . . . ,hN−1} to produce {At0h0,At1h1, . . . ,AtN−1hN−1}wherein values {h0,h1, . . . ,hN−1} are weight values selected to achieve a desired filter response and A is a factor selected to improve computational efficiency in filtering the input data stream, summing the values {At0h0,At1h1, . . .