Abstract: Some embodiments of the present invention may include a DPLL circuit comprising a firmware. The firmware may comprise a re-sampled NCO phase detector capable of receiving a reference clock timing signal and a VCXO clock timing signal. The re-sampled NCO phase detector may comprise a resampler capable of receiving phase output and the VCXO clock timing signal and resampling the phase output; and a subtractor capable of receiving the resampled phase output and subtracting the resampled phase output from a calculated mean value of the phase output. The firmware may further comprise a frequency detector capable of receiving the reference clock timing signal and the VCXO clock timing signal; and a multiplexer capable of switching between the re-sampled NCO phase detector and the frequency detector dependent upon a frequency lock status.

Abstract: Some embodiments of the present invention may include a DPLL circuit comprising a firmware. The firmware may comprise a re-sampled NCO phase detector capable of receiving a reference clock timing signal and a VCXO clock timing signal. The re-sampled NCO phase detector may comprise a resampler capable of receiving phase output and the VCXO clock timing signal and resampling the phase output; and a subtractor capable of receiving the resampled phase output and subtracting the resampled phase output from a calculated mean value of the phase output. The firmware may further comprise a frequency detector capable of receiving the reference clock timing signal and the VCXO clock timing signal; and a multiplexer capable of switching between the re-sampled NCO phase detector and the frequency detector dependent upon a frequency lock status.

Abstract: In one method embodiment, receiving a first temporal sequence of video frames, the first temporal sequence corrupted with noise; frame matching the video frames according to a first stage of processing; denoising the matched frames according to a second stage of processing, the second stage of processing commencing responsive to completion of the first stage of processing for all of the video frames, the second stage of processing comprising overlapped block processing; and wherein denoising further comprises accumulating denoised pixels for each iteration of the overlapped block processing in a two-dimensional (2D)+c accumulation buffer, the 2D accumulation buffer corresponding to the denoised pixels corresponding to a reference frame of the video frames, where c comprises an integer number of non-reference frame buffers greater than or equal to zero.