Abstract: The present invention provides a method and system of interconnecting L processors of a parallel computer to facilitate torus partitioning, (a) where each of the processors includes a processing unit and a switch, (b) where the switch includes a first external port, a second external port, a third external port, a fourth external port, a first internal port, and a second internal port, (c) where the L processors comprise R non-overlapping partitions, (d) where each of the partitions comprises the processing unit of at least one of the processors, and (e) where L is an integer ?2 and R is an integer ?1. In an exemplary embodiment, the method and system include connecting the L switches of the L processors among the external ports of the L switches in an extended torus architecture and setting the connected L switches thereby interconnecting each of the partitions as a torus.

Abstract: A method for wiring allocation and switch configuration in a multiprocessor computer, the method including employing depth-first tree traversal to determine a plurality of paths among a plurality of processing elements allocated to a job along a plurality of switches and wires in a plurality of D-lines, and selecting one of the paths in accordance with at least one selection criterion.

Abstract: The present invention provides a method and system of interconnecting L processors of a parallel computer to facilitate torus partitioning, (a) where each of the processors includes a processing unit and a switch, (b) where the switch includes a first external port, a second external port, a third external port, a fourth external port, a first internal port, and a second internal port, (c) where the L processors comprise R non-overlapping partitions, (d) where each of the partitions comprises the processing unit of at least one of the processors, and (e) where L is an integer?2 and R is an integer?1. In an exemplary embodiment, the method and system include connecting the L switches of the L processors among the external ports of the L switches in an extended torus architecture and setting the connected L switches thereby interconnecting each of the partitions as a torus.