Abstract: A wordline driver for a semiconductor memory array having a circuit for selecting and deselecting the first end of an addressed wordline and a circuit for deselecting the second end of the addressed wordline. The first and second ends of the addressed wordline are deselected at substantially the same time. The first end of the wordline is selected and deselected responsive to a strobe waveform and the second end of the wordline is deselected responsive to an RL Strobe waveform. The RL Strobe waveform is derived from a delayed strobe waveform.

Abstract: An input buffer capable of operating at a first power supply voltage level or a second power supply voltage level with the operating voltage level selectable during manufacture. At least one shortable transistor is disposed between the power supply voltage input and a buffer circuit which is connected between an input and an output of the buffer circuit. When the first voltage is the intended operating voltage the at least one shortable transistor is shorted. The first operating voltage level meets the requirements of a CMOS device and the second operating voltage level meets the requirements of a TTL device. The shortable transistor can be either a p-channel or an n-channel transistor and the short can be done by a metal layer short, a polysilicon short, a depletion implant, or with vias during manufacture.