Patents by Inventor Larry Werth

Larry Werth has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Implementations of, and methods of use for a pattern memory engine applying associative pattern memory for pattern recognition
    Patent number: 10387804
    Abstract: Computer-readable storage memory may include a) input memory having addressable blocks of random access memory storing an input data pattern, b) pattern input address memory having addressable blocks of random access memory, each of the addressable blocks storing a predetermined address of the input memory, c) current state address memory comprising a block of random access memory storing a current state address, and d) at least one next state memory having addressable blocks of random access memory, each of the addressable blocks storing predetermined data determining a next state address. The pattern input address memory and the at least one next state memory may each be sized with at least a number of addressable blocks as a maximum state address storable in the current state address memory. The current state address may index an addressable block of the pattern input address memory and the at least one next state memory.
    Type: Grant
    Filed: September 30, 2015
    Date of Patent: August 20, 2019
    Assignee: BoonLogic
    Inventor: Larry Werth
  • IMPLEMENTATIONS OF, AND METHODS OF USE FOR A PATTERN MEMORY ENGINE APPLYING ASSOCIATIVE PATTERN MEMORY FOR PATTERN RECOGNITION
    Publication number: 20160092779
    Abstract: Computer-readable storage memory may include a) input memory having addressable blocks of random access memory storing an input data pattern, b) pattern input address memory having addressable blocks of random access memory, each of the addressable blocks storing a predetermined address of the input memory, c) current state address memory comprising a block of random access memory storing a current state address, and d) at least one next state memory having addressable blocks of random access memory, each of the addressable blocks storing predetermined data determining a next state address. The pattern input address memory and the at least one next state memory may each be sized with at least a number of addressable blocks as a maximum state address storable in the current state address memory. The current state address may index an addressable block of the pattern input address memory and the at least one next state memory.
    Type: Application
    Filed: September 30, 2015
    Publication date: March 31, 2016
    Applicant: BoonLogic
    Inventor: Larry Werth