Abstract: A method and article of manufacture of a semiconductor device having a cleaned source/drain surface and substantially uniform cobalt silicide deposited thereon. The method of the invention includes a precursor conventional step of an argon ion pre-sputter step which generally cleans the semiconductor device surfaces but ensures a resputtering of SiO2 to form SiOx species deposits on the source/drain surface of the device. An in situ treatment using silicon hydride species causes reduction of the SiOx species leaving a cleaned residual silicon which can accept a cobalt deposition to form a desired cobalt silicide layer on the source/drain surface.

Abstract: A method of forming spacers in an integrated circuit is disclosed herein. The method includes providing a gate structure over a semiconductor substrate, depositing a spacer material adjacent lateral sides of the gate structure, and etching the spacer material to form spacers. The spacers have minimal surface area exposed to direct sputter.

Abstract: An article and method of manufacturing a semiconductor flash cell. The method includes producing an isolation formation layer on a silicon substrate, forming an oxide on the isolation formation layer, growing a tunnel oxide layer thereon, depositing a first poly silicon layer, masking and etching the first poly silicon layer, depositing a second poly silicon layer and performing a blanket etch back step, forming an oxide/nitride/oxide layer forming a third poly-silicon layer and depositing a silicide layer thereon.

Abstract: The quality of an ultra thin gate oxide film, particularly at the edges of a shallow trench isolation structure, is improved employing a double sacrificial oxide technique. After trench filling and planarization, the pad oxide layer thickness is increased during trench fill densification in an oxidizing atmosphere. The pad oxide is then removed exposing the substrate surface and trench edges. A second sacrificial oxide is formed consuming part of the substrate surface. The second sacrificial oxide is then removed along with defects in the substrate surface prior to gate oxide and gate electrode formation.

Abstract: The separate formation of alignment marks and manufacturing a semiconductor device comprising photolithographically printing circuit patterns is avoided by utilizing trenches formed when etching to form shallow isolation trenches, thereby increasing manufacturing throughput and reducing costs. Embodiments include utilizing alignment trenches having a depth of about 2,400.ANG. to less than about 4,000.ANG., e.g., 3,000.ANG., formed substantially simultaneously with forming isolation trenches having substantially the same depth as the alignment trenches.

Abstract: A method of forming an improved planarization mask for shallow trench isolation process area in integrated circuit manufacturing is disclosed. The planarization mask is generated automatically by using actual mask data as a reference. The invention discloses an algorithm which measures the geometric and relative separation distances of the active areas and performs the necessary merging, deletion and differential biasing to produce the planarization mask which has relaxed geometric boundaries, thereby allowing low cost and simplified manufacturing.

Abstract: A method of forming an alignment mark in a wafer during the manufacture of shallow isolation trenches for semiconductor devices provides a nitride layer on a substrate prior to the formation of the alignment mark. Once the nitride layer has been formed, etching is performed to create the alignment mark in the substrate. Further processing steps of the shallow trench isolation technique do not require the depositing of nitride into the alignment mark. Since the alignment mark is etched only after the nitride layer has been deposited, no further nitride enters into the alignment mark and a nitride-free alignment mark is provided.