Abstract: A method of manufacturing integrated circuits including a FET with a gate spacer. One embodiment provides forming a lamella of a semiconductor material and two insulator structures on opposing sides of the lamella. The lamella is recessed. A fin is formed from a central portion of the lamella. The fin is thinner than a first and a second portion of the lamella which face each other on opposing sides of the fin. A first spacer structure is formed which encompasses a first portion of the fin, the first portion adjoining to the first lamella portion. A gate electrode is disposed adjacent to the first spacer structure and encompasses a further portion of the fin on a top side and on two opposing lateral sides.

Abstract: The present invention provides a FinFET transistor arrangement produced using a method with the steps: providing a substrate (106, 108); forming an active region (1) on the substrate a fin-like channel region (113b?; 113b?). Formation of the fin-like channel region (113b?; 113b?) has the following steps: forming a hard mask (S1-S4) on the active region (1); anisotropic etching of the active region (1) using the hard mask (S1-S4) forming STI trenches (G1-G5) having an STI oxide filling (9); polishing-back of the STI oxide filling (9); etching-back of the polished-back STI oxide filling (9); selective removal of components of the hard mask forming a modified hard mask (S1?-S4?); anisotropic etching of the active region (1) using the modified hard mask (S1?-S4?) forming widened STI trenches (G1?-G5?), the fin-like channel regions (113b?; 113b?) of the active region (1) remaining for each individual FinFET transistor.

Abstract: A method of manufacturing integrated circuits including a FET with a gate spacer. One embodiment provides forming a lamella of a semiconductor material and two insulator structures on opposing sides of the lamella. The lamella is recessed. A fin is formed from a central portion of the lamella. The fin is thinner than a first and a second portion of the lamella which face each other on opposing sides of the fin. A first spacer structure is formed which encompasses a first portion of the fin, the first portion adjoining to the first lamella portion. A gate electrode is disposed adjacent to the first spacer structure and encompasses a further portion of the fin on a top side and on two opposing lateral sides.

Abstract: An integrated circuit including a memory device comprises an array portion comprising memory cells and conductive lines, an upper surface of the conductive lines being disposed beneath a surface of a semiconductor substrate, and a support portion comprising transistors of a first type, the transistors of the first type comprising a first gate electrode including vertical portions that are vertically adjacent to a channel of the transistor of the first type.

Abstract: An integrated circuit comprises a memory cell array portion and a support circuitry portion. The memory cell array portion comprises at least one bitline and at least one wordline, which is disposed above the bitline. The support circuitry portion comprises a FinFET comprising a gate electrode. An upper side of a portion of the gate electrode is disposed at the same height as an upper side of a portion of the bitline. A method of manufacturing an integrated circuit comprises the steps of forming a memory cell array and forming a support circuitry. The step of forming the memory cell array comprises forming a bitline and forming a wordline disposed above the bitline. The step of forming the support circuitry comprises forming a FinFET. The step of forming the FinFET comprises forming a gate electrode, an upper side of a portion of the gate electrode being formed at the same height as an upper side of a portion of the bitline.

Abstract: An integrated circuit including a memory device comprises an array portion comprising memory cells and conductive lines, an upper surface of the conductive lines being disposed beneath a surface of a semiconductor substrate, and a support portion comprising transistors of a first type, the transistors of the first type comprising a first gate electrode including vertical portions that are vertically adjacent to a channel of the transistor of the first type.

Abstract: A method of forming an integrated circuit, the method including forming at least one patterned gate stack on a substrate including a substrate surface; forming an amorphous substrate region in the substrate by implanting a first material in the substrate; and implanting a getter material to form a getter region within the amorphous substrate region; forming doped implant regions extending from the substrate surface in to the substrate by implanting a second material; and thermally recrystallizing the amorphous substrate region.

Abstract: An integrated circuit and method of forming an integrated circuit is disclosed. One embodiment includes a FinFET of a first type having a first gate electrode and a FinFET of a second type having a second gate electrode. The first gate electrode is formed in a gate groove that is defined in a semiconductor substrate and a bottom side of a portion of the second gate electrode is disposed above a main surface of the semiconductor substrate.

Abstract: A field effect transistor arrangement includes an electrically insulating layer, a source region, a drain region and a channel region arranged between source region and drain region, wherein the source region, the drain region and the channel region are in each case arranged on or above the electrically insulating layer, and also a gate region having an electrically insulating gate layer and an electrically conductive gate layer, which adjoins the channel region or is arranged at a distance from the latter and which extends at least partly along the channel region, wherein the source region and the drain region are in each case produced from electrically conductive carbon, and wherein the channel region is produced from strained silicon.

Abstract: Memory transistors are arranged in a plurality of rows and columns. A first source/drain terminal of each memory transistor of a first column is connected to an electrically conductive conductor track in a first metallization plane, and a first source/drain terminal of each memory transistor of a second column adjacent to the first column is connected to an electrically conductive conductor track in a second metallization plane.

Abstract: The present invention provides a production method for a FinFET transistor arrangement, and a corresponding FinFET transistor arrangement.

Abstract: Memory transistors are arranged in a plurality of rows and columns. A first source/drain terminal of each memory transistor of a first column is connected to an electrically conductive conductor track in a first metallization plane, and a first source/drain terminal of each memory transistor of a second column adjacent to the first column is connected to an electrically conductive conductor track in a second metallization plane.

Abstract: A fin field effect transistor memory cell having a first and a second source/drain region, a gate region, a semiconductor fin having a channel region between the first and the second source/drain region, a charge storage layer configured as a trapping layer arranged at least partly on the gate region, and a word line region on at least one part of the charge storage layer. The charge storage layer is set up such that electrical charge carriers can be selectively introduced into the charge storage layer or be removed therefrom by applying predetermined electrical potentials to the fin field effect transistor memory cell.