Patents by Inventor Lars-Erik Wernersson
Lars-Erik Wernersson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Vertical metal oxide semiconductor field effect transistor (MOSFET) and a method of forming the same
Patent number: 11621346Abstract: A vertical metal oxide semiconductor field effect transistor (MOSFET) and a method for forming a vertical MOSFET is presented. The MOSFET comprises: a top contact; a bottom contact; a nanowire (602) forming a charge transport channel between the top contact and the bottom contact; and a wrap-around gate (650) enclosing the nanowire (602) circumference, the wrap-around gate (650) having an extension spanning over a portion of the nanowire (602) in a longitudinal direction of the nanowire (602), wherein the wrap-around gate (650) comprises a gate portion (614) and a field plate portion (616) for controlling a charge transport in the charge transport channel, and wherein the field plate portion (616) is arranged at a first radial distance (636) from the center of the nanowire (602) and the gate portion (614) is arranged at a second radial distance (634) from the center of the nanowire (602); characterized in that the first radial distance (636) is larger than the second radial distance (634).Type: GrantFiled: May 8, 2018Date of Patent: April 4, 2023Assignee: C2AMPS ABInventors: Lars-Erik Wernersson, Olli-Pekka Kilpi -
Publication number: 20220302256Abstract: There is provided a method for fabricating an asymmetric vertical nanowire MOSFET on a semiconductor substrate comprising at least one vertical nanowire, comprising a core portion and a shell portion circumscribing the core portion. The method comprises depositing a protection layer on the semiconductor substrate, forming a top contact around a remaining portion of the vertical nanowire not covered by the protection layer, removing the protection layer, depositing a spacer layer on the semiconductor substrate, removing a shell portion of the intermediate portion of the bottom portion of the vertical nanowire, trimming a shell portion of the upper portion of the bottom portion of the vertical nanowire, depositing a metal gate on the spacer layer, and forming a lower and an upper source drain portions.Type: ApplicationFiled: September 11, 2020Publication date: September 22, 2022Inventors: Lars-Erik Wernersson, Olli-Pekka KILPI
-
Publication number: 20210280700Abstract: A vertical metal oxide semiconductor field effect transistor (MOSFET) and a method for forming a vertical MOSFET is presented. The MOSFET comprises: a top contact; a bottom contact; a nanowire (602) forming a charge transport channel between the top contact and the bottom contact; and a wrap-around gate (650) enclosing the nanowire (602) circumference, the wrap-around gate (650) having an extension spanning over a portion of the nanowire (602) in a longitudinal direction of the nanowire (602), wherein the wrap-around gate (650) comprises a gate portion (614) and a field plate portion (616) for controlling a charge transport in the charge transport channel, and wherein the field plate portion (616) is arranged at a first radial distance (636) from the center of the nanowire (602) and the gate portion (614) is arranged at a second radial distance (634) from the center of the nanowire (602); characterized in that the first radial distance (636) is larger than the second radial distance (634).Type: ApplicationFiled: May 8, 2018Publication date: September 9, 2021Inventors: Lars-Erik Wernersson, Olli-Pekka Kilpi
-
Patent number: 10361284Abstract: A method for fabrication of vertical nanowire MOSFETs is considered using a gate-last process. The top ohmic electrode is first fabricated and may be used as a mask to form a gate recess using etching techniques. The gate is thereafter formed allowing a large degree in access resistance reduction.Type: GrantFiled: June 21, 2016Date of Patent: July 23, 2019Inventors: Lars-Erik Wernersson, Johannes Svensson, Martin Berg, Karl-Magnus Persson, Erik Lind
-
Publication number: 20180358225Abstract: A method for fabrication of growing, in one growth run, at least one group of III-V n-type nanowires and at least one group of III-V p-type nanowires using gold particles, where the gold particles are of one size for the III-V n-type nanowires and one size for the III-V p-type nanowires.Type: ApplicationFiled: May 27, 2016Publication date: December 13, 2018Inventor: Lars-Erik WERNERSSON
-
Patent number: 10090292Abstract: A radial nanowire Esaki diode device includes a semiconductor core of a first conductivity type and a semiconductor shell of a second conductivity type different from the first conductivity type. The device may be a TFET or a solar cell.Type: GrantFiled: July 5, 2013Date of Patent: October 2, 2018Assignee: QUNANO ABInventors: Lars-Erik Wernersson, Erik Lind, Jonas Ohlsson, Lars Samuelson, Mikeal Bjork, Claes Thelander, Anil Dey
-
Publication number: 20180219084Abstract: A method for fabrication of vertical nanowire MOSFETs is considered using a gate-last process. The top ohmic electrode is first fabricated and may be used as a mask to form a gate recess using etching techniques. The gate is thereafter formed allowing a large degree in access resistance reduction.Type: ApplicationFiled: June 21, 2016Publication date: August 2, 2018Inventors: Lars-Erik Wernersson, Johannes Svensson, Martin Berg, Karl-Magnus Persson, Erik Lind
-
Patent number: 9608567Abstract: A transceiver comprising a tank circuit, a variable differential conductance, VDC, coupled to the tank circuit, and a variable resistance coupled to the VDC is disclosed. The variable resistance is arranged to bias the VDC into a region of positive differential conductance during a first state of operation of the transceiver, and bias the VDC into a region of negative differential conductance during a second state of operation of the transceiver.Type: GrantFiled: May 30, 2011Date of Patent: March 28, 2017Assignee: Acconeer ABInventors: Mikael Egard, Mats Ärlelid, Lars-Erik Wernersson
-
Patent number: 9117753Abstract: According to one aspect of the inventive concept there is provided a process for manufacturing a semiconductor device, comprising: providing a channel layer (104), providing a mask (106) on the channel layer, epitaxially growing a contact layer (108) in contact with the channel layer, epitaxially growing a support layer (110) on the contact layer, wherein the support layer is arranged to be etched at a higher rate than the contact layer, forming a trench extending through the support layer by removing the mask, and providing a conductor (118) in the trench. There is also provided an intermediate product for the manufacture of a semiconductor device.Type: GrantFiled: June 1, 2012Date of Patent: August 25, 2015Assignee: Acconeer ABInventors: Mikael Egard, Erik Lind, Lars-Erik Wernersson
-
Patent number: 9087896Abstract: The present invention relates to providing layers of different thickness on vertical and horizontal surfaces (15, 20) of a vertical semiconductor device (1). In particular the invention relates to gate electrodes and the formation of precision layers (28) in semiconductor structures comprising a substrate (10) and an elongated structure (5) essentially standing up from the substrate. According to the method of the invention the vertical geometry of the device (1) is utilized in combination with either anisotropic deposition or anisotropic removal of deposited material to form vertical or horizontal layers of very high precision.Type: GrantFiled: October 8, 2013Date of Patent: July 21, 2015Assignee: QUNANO ABInventors: Jonas Ohlsson, Lars Samuelson, Erik Lind, Lars-Erik Wernersson, Truls Lowgren
-
Publication number: 20150171076Abstract: A radial nanowire Esaki diode device includes a semiconductor core of a first conductivity type and a semiconductor shell of a second conductivity type different from the first conductivity type. The device may be a TFET or a solar cell.Type: ApplicationFiled: July 5, 2013Publication date: June 18, 2015Inventors: Lars-Erik Wernersson, Erik Lind, Jonas Ohlsson, Lars Samuelson, Mikeal Bjork, Claes Thelander, Anil Dey
-
Patent number: 8890117Abstract: A nanowire circuit architecture is presented. The technology comprises of nanowire transistors (8,9), and optionally nanowire capacitors (12) and nanowire resistors (11), that are integrated using two levels of interconnects only (1,2). Implementations of ring-oscillators, sample-and-hold circuits, and comparators may be realized in this nanowire circuit architecture. Circuit input and circuit output as well as the transistor connections within each circuit are provided in the two levels of interconnects (1,2).Type: GrantFiled: March 28, 2008Date of Patent: November 18, 2014Assignee: Qunano ABInventor: Lars-Erik Wernersson
-
Publication number: 20140103423Abstract: The present invention relates to providing layers of different thickness on vertical and horizontal surfaces (15, 20) of a vertical semiconductor device (1). In particular the invention relates to gate electrodes and the formation of precision layers (28) in semiconductor structures comprising a substrate (10) and an elongated structure (5) essentially standing up from the substrate. According to the method of the invention the vertical geometry of the device (1) is utilized in combination with either anisotropic deposition or anisotropic removal of deposited material to form vertical or horizontal layers of very high precision.Type: ApplicationFiled: October 8, 2013Publication date: April 17, 2014Applicant: QUNANO ABInventors: Jonas Ohlsson, Lars Samuelson, Erik Lind, Lars-Erik Wernersson, Truls Lowgren
-
Publication number: 20140106553Abstract: According to one aspect of the inventive concept there is provided a process for manufacturing a semiconductor device, comprising: providing a channel layer (104), providing a mask (106) on the channel layer, epitaxially growing a contact layer (108) in contact with the channel layer, epitaxially growing a support layer (110) on the contact layer, wherein the support layer is arranged to be etched at a higher rate than the contact layer, forming a trench extending through the support layer by removing the mask, and providing a conductor (118) in the trench. There is also provided an intermediate product for the manufacture of a semiconductor device.Type: ApplicationFiled: June 1, 2012Publication date: April 17, 2014Applicant: ACCONEER ABInventors: Mikael Egard, Erik Lind, Lars-Erik Wernersson
-
Publication number: 20140098845Abstract: A transceiver comprising a tank circuit, a variable differential conductance, VDC, coupled to the tank circuit, and a variable resistance coupled to the VDC is disclosed. The variable resistance is arranged to bias the VDC into a region of positive differential conductance during a first state of operation of the transceiver, and bias the VDC into a region of negative differential conductance during a second state of operation of the transceiver.Type: ApplicationFiled: May 30, 2011Publication date: April 10, 2014Applicant: ACCONEER ABInventors: Mikael Egard, Mats Ärlelid, Lars-Erik Wernersson
-
Publication number: 20140048851Abstract: The present invention relates to a substrate (5) comprising a Si-base (1) and an InAs-layer (4) provided on said Si-base where said InAs-layer (4) has a thickness between 100 and 500 nanometers and root-mean-square roughness of the upper surface of said InAs-layer (4) is below 1 nanometer. The invention further relates to a method for forming said substrate. The invention also relates to growing InAs-nanowires (7) as well as a GaSb-layer (17) on said substrate (5).Type: ApplicationFiled: April 27, 2012Publication date: February 20, 2014Applicant: QUNANO ABInventors: Lars-Erik Wernersson, Sepideh Ghalamestani
-
Patent number: 8551834Abstract: The present invention relates to providing layers of different thickness on vertical and horizontal surfaces (15, 20) of a vertical semiconductor device (1). In particular the invention relates to gate electrodes and the formation of precision layers (28) in semiconductor structures comprising a substrate (10) and an elongated structure (5) essentially standing up from the substrate. According to the method of the invention the vertical geometry of the device (1) is utilized in combination with either anisotropic desposition or anisotropic removal of deposited material to form vertical or horizontal layers of very high precision.Type: GrantFiled: April 27, 2012Date of Patent: October 8, 2013Assignee: QuNano ABInventors: Jonas Ohlsson, Lars Samuelson, Erik Lind, Lars-Erik Wernersson, Truls Lowgren
-
Patent number: 8344361Abstract: The present invention relates to nanoscaled electronic devices with a vertical nanowire as a functional part. Contacts are arranged on the nanowire at different parts of the nanowire, for example drain and source contacts. In connection to the nanowire contacts are external electrodes, that connect at different levels, as seen from the substrate, of the device. The external electrodes are elongated, and typically and preferably stripe-like. According to the invention a first external electrode, or contacts, associated with contact(s) at a first part of the nanowire, and a second external electrode, associated with contact(s) at a second part of the nanowire are arranged in a cross-bar configuration. The cross-bar configuration minimizes the overlay of the external electrodes, hence, parasitic capacitances and current leakage can be reduced, and the performance of the device improved.Type: GrantFiled: June 16, 2006Date of Patent: January 1, 2013Assignee: QuNano ABInventors: Lars-Erik Wernersson, Tomas Bryllert, Erik Lind, Lars Samuelson
-
Patent number: 8330143Abstract: A nanowire wrap-gate transistor is realized in a semiconductor material with a band gap narrower than Si. The strain relaxation in the nanowires allows the transistor to be placed on a large variety of substrates and heterostructures to be incorporated in the device. Various types of heterostructures should be introduced in the transistor to reduce the output conductance via reduced impact ionization rate, increase the current on/off ratio, reduction of the sub-threshold slope, reduction of transistor contact resistance and improved thermal stability. The parasitic capacitances should be minimized by the use of semi-insulating substrates and the use of cross-bar geometry between the source and drain access regions. The transistor may find applications in digital high frequency and low power circuits as well as in analogue high frequency circuits.Type: GrantFiled: June 16, 2006Date of Patent: December 11, 2012Assignee: QuNano ABInventors: Lars-Erik Wernersson, Tomas Bryllert, Erik Lind, Lars Samuelson
-
Publication number: 20120211727Abstract: The present invention relates to providing layers of different thickness on vertical and horizontal surfaces (15, 20) of a vertical semiconductor device (1). In particular the invention relates to gate electrodes and the formation of precision layers (28) in semiconductor structures comprising a substrate (10) and an elongated structure (5) essentially standing up from the substrate. According to the method of the invention the vertical geometry of the device (1) is utilized in combination with either anisotropic desposition or anisotropic removal of deposited material to form vertical or horizontal layers of very high precision.Type: ApplicationFiled: April 27, 2012Publication date: August 23, 2012Applicant: QuNano ABInventors: Jonas Ohlsson, Lars Samuelson, Erik Lind, Lars-Erik Wernersson, Truls Löwgren