Patents by Inventor Lars Heineck
Lars Heineck has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10566332Abstract: A semiconductor memory device includes a semiconductor substrate having active areas and a trench isolation region between the active areas. The active areas extend along a first direction. Buried word lines extend along a second direction in the semiconductor substrate. Two of the buried word lines intersect with each of the active areas, separating each of the active areas into a digit line contact area and two cell contact areas. The second direction is not perpendicular to the first direction. A digit line contact is disposed on the digit line contact area. A storage node contact is disposed on each of the two cell contact areas. The digit line contact and the storage node contact are coplanar. At least one digit line extends along a third direction over a main surface of the semiconductor substrate. The at least one digit line is in direct contact with the digit line contact.Type: GrantFiled: November 15, 2018Date of Patent: February 18, 2020Assignee: Micron Technology, Inc.Inventors: Kuo-Chen Wang, Shih-Fan Kuan, Lars Heineck, Sanh D. Tang
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Publication number: 20190088658Abstract: A semiconductor memory device includes a semiconductor substrate having active areas and a trench isolation region between the active areas. The active areas extend along a first direction. Buried word lines extend along a second direction in the semiconductor substrate. Two of the buried word lines intersect with each of the active areas, separating each of the active areas into a digit line contact area and two cell contact areas. The second direction is not perpendicular to the first direction. A digit line contact is disposed on the digit line contact area. A storage node contact is disposed on each of the two cell contact areas. The digit line contact and the storage node contact are coplanar. At least one digit line extends along a third direction over a main surface of the semiconductor substrate. The at least one digit line is in direct contact with the digit line contact.Type: ApplicationFiled: November 15, 2018Publication date: March 21, 2019Inventors: Kuo-Chen Wang, Shih-Fan Kuan, Lars Heineck, Sanh D. Tang
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Patent number: 10163909Abstract: A semiconductor memory device includes a semiconductor substrate having active areas and a trench isolation region between the active areas. The active areas extend along a first direction. Buried word lines extend along a second direction in the semiconductor substrate. Two of the buried word lines intersect with each of the active areas, separating each of the active areas into a digit line contact area and two cell contact areas. The second direction is not perpendicular to the first direction. A digit line contact is disposed on the digit line contact area. A storage node contact is disposed on each of the two cell contact areas. The digit line contact and the storage node contact are coplanar. At least one digit line extends along a third direction over a main surface of the semiconductor substrate. The at least one digit line is in direct contact with the digit line contact.Type: GrantFiled: December 13, 2017Date of Patent: December 25, 2018Assignee: Micron Technology, Inc.Inventors: Kuo-Chen Wang, Shih-Fan Kuan, Lars Heineck, Sanh Tang
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Publication number: 20180102366Abstract: A semiconductor memory device includes a semiconductor substrate having active areas and a trench isolation region between the active areas. The active areas extend along a first direction. Buried word lines extend along a second direction in the semiconductor substrate. Two of the buried word lines intersect with each of the active areas, separating each of the active areas into a digit line contact area and two cell contact areas. The second direction is not perpendicular to the first direction. A digit line contact is disposed on the digit line contact area. A storage node contact is disposed on each of the two cell contact areas. The digit line contact and the storage node contact are coplanar. At least one digit line extends along a third direction over a main surface of the semiconductor substrate. The at least one digit line is in direct contact with the digit line contact.Type: ApplicationFiled: December 13, 2017Publication date: April 12, 2018Inventors: Kuo-Chen Wang, Shih-Fan Kuan, Lars Heineck, Sanh Tang
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Patent number: 9881924Abstract: A semiconductor memory device includes a semiconductor substrate having active areas and a trench isolation region between the active areas. The active areas extend along a first direction. Buried word lines extend along a second direction in the semiconductor substrate. Two of the buried word lines intersect with each of the active areas, separating each of the active areas into a digit line contact area and two cell contact areas. The second direction is not perpendicular to the first direction. A digit line contact is disposed on the digit line contact area. A storage node contact is disposed on each of the two cell contact areas. The digit line contact and the storage node contact are coplanar. At least one digit line extends along a third direction over a main surface of the semiconductor substrate. The at least one digit line is in direct contact with the digit line contact.Type: GrantFiled: May 11, 2016Date of Patent: January 30, 2018Assignee: Micron Technology, Inc.Inventors: Kuo-Chen Wang, Shih-Fan Kuan, Lars Heineck, Sanh Tang
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Publication number: 20170330882Abstract: A semiconductor memory device includes a semiconductor substrate having active areas and a trench isolation region between the active areas. The active areas extend along a first direction. Buried word lines extend along a second direction in the semiconductor substrate. Two of the buried word lines intersect with each of the active areas, separating each of the active areas into a digit line contact area and two cell contact areas. The second direction is not perpendicular to the first direction. A digit line contact is disposed on the digit line contact area. A storage node contact is disposed on each of the two cell contact areas. The digit line contact and the storage node contact are coplanar. At least one digit line extends along a third direction over a main surface of the semiconductor substrate. The at least one digit line is in direct contact with the digit line contact.Type: ApplicationFiled: May 11, 2016Publication date: November 16, 2017Inventors: Kuo-Chen Wang, Shih-Fan Kuan, Lars Heineck, Sanh Tang
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Patent number: 9691773Abstract: An access device includes a plurality of first digit lines (DL) trenches extending along a first direction, buried digit lines between each DL trench, second and third trenches separating the digit lines, a filling material filling the digit line trenches comprising airgaps in each second trench, a plurality of word line (WL) trenches extending along a second direction, metal word lines deposited on the walls of the word line trenches, a filling material filling the word line trenches.Type: GrantFiled: November 1, 2013Date of Patent: June 27, 2017Assignee: NANYA TECHNOLOGY CORP.Inventors: Shyam Surthi, Lars Heineck
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Patent number: 9337201Abstract: A memory cell includes a vertically oriented transistor having an elevationally outer source/drain region, an elevationally inner source/drain region, and a channel region elevationally between the inner and outer source/drain regions. The inner source/drain region has opposing laterally outer sides. One of a pair of data/sense lines is electrically coupled to and against one of the outer sides of the inner source/drain region. The other of the pair of data/sense lines is electrically coupled to and against the other of the outer sides of the inner source/drain region. An access gate line is elevationally outward of the pair of electrically coupled data/sense lines and is operatively adjacent the channel region. A charge storage device is electrically coupled to the outer source/drain region. Other embodiments and additional aspects, including methods, are disclosed.Type: GrantFiled: September 12, 2012Date of Patent: May 10, 2016Assignee: Micron Technology, Inc.Inventors: Lars Heineck, Jaydip Guha
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Patent number: 9263317Abstract: A method of forming a buried word line structure is provided. A first mask layer, an interlayer and a second mask layer are sequentially formed on a substrate, wherein the second mask layer has a plurality of mask patterns and a plurality of gaps arranged alternately, and the gaps includes first gaps and second gaps arranged alternately. A dielectric pattern is formed in each first gap and spacers are simultaneously formed on sidewalls of each second gap, wherein a first trench is formed between the adjacent spacers and exposes a portion of the first mask layer. The mask patterns are removed to form second trenches. An etching process is performed by using the dielectric patterns and the spacers as a mask, so that the first trenches are deepened to the substrate and the second trenches are deepened to the first mask layer.Type: GrantFiled: March 28, 2014Date of Patent: February 16, 2016Assignee: NANYA TECHNOLOGY CORPORATIONInventors: Inho Park, Lars Heineck
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Patent number: 9070584Abstract: A memory array includes a plurality of digitline (DL) trenches extending along a first direction; a buried digitline between the DL trenches; a trench fill material layer sealing an air gap in each of the DL trenches; a plurality of wordline (WL) trenches extending along a second direction; an active chop (AC) trench disposed at one end of the buried digitline; a shield layer in the air gap; and a sidewall conductor around the sidewall of the AC trench.Type: GrantFiled: May 24, 2013Date of Patent: June 30, 2015Assignee: NANYA TECHNOLOGY CORP.Inventors: Shyam Surthi, Lars Heineck
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Publication number: 20150123280Abstract: An access device includes a plurality of first digit lines (DL) trenches extending along a first direction, buried digit lines between each DL trench, second and third trenches separating the digit lines, a filling material filling the digit line trenches comprising airgaps in each second trench, a plurality of word line (WL) trenches extending along a second direction, metal word lines deposited on the walls of the word line trenches, a filling material filling the word line trenches.Type: ApplicationFiled: November 1, 2013Publication date: May 7, 2015Applicant: NANYA TECHNOLOGY CORP.Inventors: Shyam Surthi, Lars Heineck
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Patent number: 9012330Abstract: The present invention provides a method of cross double pitch patterning for forming a contact printing mask. First, a first, a second and a third layer a successively deposited; a photoresist is deposited on the third layer, and then trimmed into a first pre-pattern, on which an oxide layer is deposited. The oxide layer is etched into spacers forming a first pattern that is then etched into the third layer. A second cross pattern is formed the same way on the third layer. Finally the first and second layers are etched with selectivity both patterns.Type: GrantFiled: August 22, 2013Date of Patent: April 21, 2015Assignee: Nanya Technology Corp.Inventors: Vinay Nair, Lars Heineck
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Publication number: 20150056810Abstract: The present invention provides a method of cross double pitch patterning for forming a contact printing mask. First, a first, a second and a third layer a successively deposited; a photoresist is deposited on the third layer, and then trimmed into a first pre-pattern, on which an oxide layer is deposited. The oxide layer is etched into spacers forming a first pattern that is then etched into the third layer. A second cross pattern is formed the same way on the third layer. Finally the first and second layers are etched with selectivity both patterns.Type: ApplicationFiled: August 22, 2013Publication date: February 26, 2015Applicant: NANYA TECHNOLOGY CORP.Inventors: Vinay Nair, Lars Heineck
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Publication number: 20140346652Abstract: A memory array includes a plurality of digitline (DL) trenches extending along a first direction; a buried digitline between the DL trenches; a trench fill material layer sealing an air gap in each of the DL trenches; a plurality of wordline (WL) trenches extending along a second direction; an active chop (AC) trench disposed at one end of the buried digitline; a shield layer in the air gap; and a sidewall conductor around the sidewall of the AC trench.Type: ApplicationFiled: May 24, 2013Publication date: November 27, 2014Applicant: NANYA TECHNOLOGY CORP.Inventors: Shyam Surthi, Lars Heineck
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Publication number: 20140213035Abstract: A method of forming a buried word line structure is provided. A first mask layer, an interlayer and a second mask layer are sequentially formed on a substrate, wherein the second mask layer has a plurality of mask patterns and a plurality of gaps arranged alternately, and the gaps includes first gaps and second gaps arranged alternately. A dielectric pattern is formed in each first gap and spacers are simultaneously formed on sidewalls of each second gap, wherein a first trench is formed between the adjacent spacers and exposes a portion of the first mask layer. The mask patterns are removed to form second trenches. An etching process is performed by using the dielectric patterns and the spacers as a mask, so that the first trenches are deepened to the substrate and the second trenches are deepened to the first mask layer.Type: ApplicationFiled: March 28, 2014Publication date: July 31, 2014Applicant: NANYA TECHNOLOGY CORPORATIONInventors: Inho Park, Lars Heineck
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Publication number: 20140159140Abstract: A method of forming a buried word line structure is provided. A first mask layer, an interlayer and a second mask layer are sequentially formed on a substrate, wherein the second mask layer has a plurality of mask patterns and a plurality of gaps arranged alternately, and the gaps includes first gaps and second gaps arranged alternately. A dielectric pattern is formed in each first gap and spacers are simultaneously formed on sidewalls of each second gap, wherein a first trench is formed between the adjacent spacers and exposes a portion of the first mask layer. The mask patterns are removed to form second trenches. An etching process is performed by using the dielectric patterns and the spacers as a mask, so that the first trenches are deepened to the substrate and the second trenches are deepened to the first mask layer.Type: ApplicationFiled: December 6, 2012Publication date: June 12, 2014Inventors: Inho Park, Lars Heineck
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Patent number: 8735267Abstract: A method of forming a buried word line structure is provided. A first mask layer, an interlayer and a second mask layer are sequentially formed on a substrate, wherein the second mask layer has a plurality of mask patterns and a plurality of gaps arranged alternately, and the gaps includes first gaps and second gaps arranged alternately. A dielectric pattern is formed in each first gap and spacers are simultaneously formed on sidewalls of each second gap, wherein a first trench is formed between the adjacent spacers and exposes a portion of the first mask layer. The mask patterns are removed to form second trenches. An etching process is performed by using the dielectric patterns and the spacers as a mask, so that the first trenches are deepened to the substrate and the second trenches are deepened to the first mask layer.Type: GrantFiled: December 6, 2012Date of Patent: May 27, 2014Assignee: Nanya Technology CorporationInventors: Inho Park, Lars Heineck
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Publication number: 20140042548Abstract: A DRAM structure with buried word lines is described, including a semiconductor substrate, cell word lines buried in the substrate and separated from the same by a first gate dielectric layer, and isolation word lines buried in the substrate and separated from the same by a second gate dielectric layer. The top surfaces of the cell word lines and those of the isolation word lines are lower than the top surface of the substrate. The bottom surfaces of the isolation word lines are lower than those of the cell word lines.Type: ApplicationFiled: October 7, 2013Publication date: February 13, 2014Applicant: NANYA TECHNOLOGY CORPORATIONInventors: Hao-Chieh Liu, Lars Heineck, Ping-Chieh Chiang
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Patent number: 8502294Abstract: A semiconductor process for a memory array with buried digit lines is described. A first trench is formed in a semiconductor substrate. A liner layer is formed on the sidewall of the first trench. A second trench is formed in the substrate under the first trench. A mask layer is formed at the bottom of the second trench. An isotropic doping process is performed using the liner layer and the mask layer as a mask to form a digit-side junction only in the substrate at the sidewall of the second trench.Type: GrantFiled: May 15, 2012Date of Patent: August 6, 2013Assignee: Nanya Technology CorporationInventors: Shyam Surthi, Lars Heineck
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Patent number: 8450207Abstract: The present invention proposes the use of a silicon nitride layer on top of a second conductive layer. After a step of etching a second conductive layer, an oxide spacer is formed to define a gap. Then, another silicon nitride layer fills up the gap. After that, the oxide spacer is removed. Later, a first conductive layer is etched to separate the digit line to cell contact line.Type: GrantFiled: June 21, 2011Date of Patent: May 28, 2013Assignee: Nanya Technology Corp.Inventors: Shyam Surthi, Lars Heineck