Abstract: A system having a load that generates an EMF energy, comprising: a controller; a switch having a control terminal coupled to the controller and a second terminal coupled to the load; a recycling circuit coupled to the load and the second terminal of the switch, the recycling circuit including a capacitor and a converter coupled to the capacitor, a voltage source and the load; and wherein the capacitor is operable to store the EMF energy.

Abstract: A system having a load that generates an EMF energy, comprising: a controller; a switch having a control terminal coupled to the controller and a second terminal coupled to the load; a recycling circuit coupled to the load and the second terminal of the switch, the recycling circuit including a capacitor and a converter coupled to the capacitor, a voltage source and the load; and wherein the capacitor is operable to store the EMF energy.

Abstract: In some examples, a device comprises a capacitor a bidirectional inverting buck-boost converter coupled to the capacitor and configured to couple to multiple loads and to a voltage source, wherein the bidirectional inverting buck-boost converter is configured to: compare a voltage across the capacitor with a reference voltage; and based on the comparison, facilitate converting a dissipation current flowing from one of the multiple loads into a recycling current.

Abstract: In some examples, a device comprises a capacitor a bidirectional inverting buck-boost converter coupled to the capacitor and configured to couple to multiple loads and to a voltage source, wherein the bidirectional inverting buck-boost converter is configured to: compare a voltage across the capacitor with a reference voltage; and based on the comparison, facilitate converting a dissipation current flowing from one of the multiple loads into a recycling current.

Abstract: A reduced-pin bus system includes a bus having one or more signal lines that are coupled to a bus power supply through a current limiting device. A master unit is coupled to the bus and is arranged to transmit communications across the bus during an active period of the bus and to initiate communications during (and/or at the end of) a quiescent period of the bus. A slave unit is coupled to the bus and is arranged to couple power from the one or more signal lines to a capacitor during the quiescent period of the bus and to consume power from the capacitor during the active period of the bus.

Abstract: A prescaling counter includes a prescaling unit and a counter. The prescaling unit includes a programmable divider that is arranged to divide an event clock that includes signaled events to generate a prescaled clock in response to a prescaling value. The counter includes a register that includes a lower count register and an upper count register for generating a count result. The counter is arranged to increment the lower count register in response to the prescaled clock and to increment the upper count register in response to a terminal condition in the lower count register. The prescaling value is generated in response to the upper count register.

Abstract: A reduced-pin bus system includes a bus having one or more signal lines that are coupled to a bus power supply through a current limiting device. A master unit is coupled to the bus and is arranged to transmit communications across the bus during an active period of the bus and to initiate communications during (and/or at the end of) a quiescent period of the bus. A slave unit is coupled to the bus and is arranged to couple power from the one or more signal lines to a capacitor during the quiescent period of the bus and to consume power from the capacitor during the active period of the bus.

Abstract: A prescaling counter includes a prescaling unit and a counter. The prescaling unit includes a programmable divider that is arranged to divide an event clock that includes signaled events to generate a prescaled clock in response to a prescaling value. The counter includes a register that includes a lower count register and an upper count register for generating a count result. The counter is arranged to increment the lower count register in response to the prescaled clock and to increment the upper count register in response to a terminal condition in the lower count register. The prescaling value is generated in response to the upper count register.

Abstract: An integrated circuit (IC) configured to operate as a slave on an inter-integrated circuit (I2C) or I2C compatible bus. The IC is further configured to receive an address through the I2C bus and store the received address in a register, so as to be identified by the address. A method of address assignment in a master/slave system, the system comprises at least one master, a plurality of slaves, and an I2C or I2C compatible bus. The method comprises sending a first address by the master on the I2C bus to a first of the plurality of slaves and storing the first address on the first slave to identify the first slave by the first address. The method further comprises sending a second address by the master on the I2C bus to a second of the plurality of slaves and storing the second address on the second slave to identify the second slave by the second address. The steps of sending and storing are repeated until all slaves of the system have stored an address.

Abstract: An integrated circuit (IC) configured to operate as a slave on an inter-integrated circuit (I2C) or I2C compatible bus. The IC is further configured to receive an address through the I2C bus and store the received address in a register, so as to be identified by the address. A method of address assignment in a master/slave system, the system comprises at least one master, a plurality of slaves, and an I2C or I2C compatible bus. The method comprises sending a first address by the master on the I2C bus to a first of the plurality of slaves and storing the first address on the first slave to identify the first slave by the first address. The method further comprises sending a second address by the master on the I2C bus to a second of the plurality of slaves and storing the second address on the second slave to identify the second slave by the second address. The steps of sending and storing are repeated until all slaves of the system have stored an address.