Patents by Inventor Lars Mueller
Lars Mueller has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12269768Abstract: A cover glass is provided that includes a silica based glass ceramic with a thickness between 0.4 mm and 0.85 mm. The glass ceramic has a transmittance of more than 80% from 380 nm to 780 nm and a stress attribute selected from: an overall compressive stress (CS) of at least 250 MPa and at most 1500 MPa, a compressive stress at a depth of 30 ?m (CS30) from one of the two faces of at least 160 MPa and at most 525 MPa, a depth of the compression layer (DoCL) of at least 0.2 times the thickness and less than 0.5 times the thickness, and any combinations thereof. The glass ceramic has at least one silica based crystal phase having in a near-surface layer a unit cell volume of at least 1% by volume larger than that of a core where the crystal phase has minimum stresses.Type: GrantFiled: December 12, 2022Date of Patent: April 8, 2025Assignees: SCHOTT AG, SCHOTT TECHNICAL GLASS SOLUTIONS GMBHInventors: Ruediger Dietrich, Bernd Ruedinger, Meike Schneider, Jochen Alkemper, Lars Mueller, Thomas Pfeiffer, Julian Koch
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Patent number: 12211785Abstract: A multi-voltage domain device includes a semiconductor layer including a first main surface, a second main surface arranged opposite to the first main surface, a first region including first circuitry that operates in a first voltage domain, a second region including second circuitry that operates in a second voltage domain different than the first voltage domain, and an isolation region that electrically isolates the first region from the second region in a lateral direction that extends parallel to the first and the second main surfaces. The isolation region includes at least one deep trench isolation barrier, each of which extends vertically from the first main surface to the second main surface. The multi-voltage domain device further includes at least one first capacitor configured to generate an electric field laterally across the isolation region between the first region and the second region.Type: GrantFiled: February 21, 2023Date of Patent: January 28, 2025Assignee: Infineon Technologies Austria AGInventors: Lars Mueller-Meskamp, Berthold Astegher, Hermann Gruber, Thomas Christian Neidhart
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Publication number: 20240424209Abstract: Systems and methods are provided for determining patterns, trends, anomalies, and/or abnormalities in data relating to operation of an insulin delivery pump and user outcomes relating to an insulin delivery pump and determining certain actions and/or operational adjustments to improve the user outcomes, such as blood glucose levels. For example, troubleshooting actions may be recommended upon determining a pattern, trend, abnormality, and/or anomaly in blood glucose levels that is undesirable. In another example, operation of the insulin delivery pump may be adjusted based habits and/or behaviors of the user. For example, insulin delivery timing may be adjusted based on exercise, activity and/or eating patterns. Based on the detected patterns, trends, anomalies, and/or abnormalities, a user device such as a mobile phone or smart device may present prompts for more information, alerts, status updates, and other information intended to improve the user experience.Type: ApplicationFiled: June 20, 2024Publication date: December 26, 2024Inventors: Alexandra Elena CONSTANTIN, Alex TRAHAN, Lars MUELLER, Zahra YARMOHAMMADI, Gina MERCHANT, Daphna ZEILINGOLD
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Publication number: 20240363699Abstract: A semiconductor device includes: a semiconductor substrate having a first main surface and a second main surface opposite the first main surface; and a trench structure extending into the semiconductor substrate from the first main surface. The trench structure includes: an upper section extending into the semiconductor substrate from the first main surface; a lower section at an opposite end of the trench structure as the upper section; a first intermediary section between the upper section and the lower section; a field plate in the upper section and dielectrically insulated from the semiconductor substrate; and a first dielectric material completely filling the lower section. The lower section, the upper section, and the first intermediary section have different geometries and/or different dielectric materials. Methods of producing the semiconductor device are also described.Type: ApplicationFiled: April 27, 2023Publication date: October 31, 2024Inventors: Annett Winzer, Lars Mueller-Meskamp, Tom Peterhaensel, Fabian Geisenhof, Torsten Helm, Dirk Manger
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Publication number: 20240363700Abstract: A semiconductor device includes: a silicon layer having an electrically insulated backside and a thickness in a range of 10 ?m to 200 ?m between a frontside of the silicon layer and the electrically insulated backside; a high voltage region and a low voltage region formed in the silicon layer and laterally spaced apart from one another; and a first field plate structure extending from the frontside into the silicon layer. The first field plate structure includes a field plate laterally separated from the silicon layer by a dielectric material and/or a pn junction.Type: ApplicationFiled: April 28, 2023Publication date: October 31, 2024Inventors: Lars Mueller-Meskamp, Ralf Rudolf, Anton Mauder, Annett Winzer, Dirk Priefert, Christian Schippel, Thomas Kuenzig
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Publication number: 20240290882Abstract: A semiconductor device includes: a silicon layer having a frontside and an electrically insulated backside; a first trench extending through the silicon layer from the frontside to the electrically insulated backside and laterally isolating a first region of the silicon layer; an electrically conductive material in the first trench; a dielectric material separating the electrically conductive material from silicon material of the silicon layer; and a plurality of silicon plugs laterally surrounded by the dielectric material and dividing the electrically conductive material into a plurality of separate segments in the first trench. Additional embodiments of semiconductor devices and methods for manufacturing the semiconductor devices are also described.Type: ApplicationFiled: February 23, 2023Publication date: August 29, 2024Inventors: Annett Winzer, Lars Mueller-Meskamp, Ralf Rudolf, Tom Peterhaensel, Birgit von Ehrenwall, Frido Erler, Dirk Manger
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Publication number: 20230411060Abstract: A semiconductor die includes: a semiconductor substrate; a transmitter or receiver circuit in the semiconductor substrate; a multi-layer stack on the semiconductor substrate, the multi-layer stack including a plurality of metallization layers separated from one another by an interlayer dielectric; and a transformer in the multi-layer stack and electrically coupled to the transmitter or receiver circuit. The transformer includes a first winding formed in a first metallization layer of the plurality of metallization layers and a second winding formed in a second metallization layer of the plurality of metallization layers. The first winding and the second winding are inductively coupled to one another. A magnetic material in the multi-layer stack is adjacent to at least part of the transformer.Type: ApplicationFiled: June 20, 2022Publication date: December 21, 2023Inventors: Annett Winzer, Michael Kirsch, Lars Mueller-Meskamp
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Patent number: 11768264Abstract: A method for multi-dimensional, relaxation-diffusion magnetic resonance fingerprinting (MRF) includes performing, using a magnetic resonance imaging (MRI) system, a pulse sequence that integrates free-waveform b-tensor diffusion encoding into a magnet resonance fingerprinting pulse sequence to perform a multi-dimensional, relaxation-diffusion encoding while acquiring MRF signal evolutions, processing, using a processor, the acquired MRF signal evolutions to determine at least one relaxation parameter and at least one diffusivity parameter, and generating, using the processor, a report including at least one of the at least one relaxation parameter and the at least diffusivity parameter.Type: GrantFiled: May 2, 2022Date of Patent: September 26, 2023Assignees: Case Western Reserve University, University College Cardiff Consultants Limited CardiffInventors: Dan Ma, Mark A. Griswold, Derek Jones, Maryam Afzali, Lars Mueller
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Publication number: 20230207451Abstract: A multi-voltage domain device includes a semiconductor layer including a first main surface, a second main surface arranged opposite to the first main surface, a first region including first circuitry that operates in a first voltage domain, a second region including second circuitry that operates in a second voltage domain different than the first voltage domain, and an isolation region that electrically isolates the first region from the second region in a lateral direction that extends parallel to the first and the second main surfaces. The isolation region includes at least one deep trench isolation barrier, each of which extends vertically from the first main surface to the second main surface. The multi-voltage domain device further includes at least one first capacitor configured to generate an electric field laterally across the isolation region between the first region and the second region.Type: ApplicationFiled: February 21, 2023Publication date: June 29, 2023Inventors: Lars MUELLER-MESKAMP, Berthold ASTEGHER, Hermann GRUBER, Thomas Christian NEIDHART
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Publication number: 20230183127Abstract: A cover glass made of a glass ceramic that is silica based and has a main crystal phase of high quartz solid solution or keatite solid solution is provided. The cover glass has a stress profile with at least one inflection point at a depth of the cover glass of more than 10 ?m, a thickness from 0.1 mm to 2 mm, and a chemical tempering structure with a surface compressive stress of at least 250 MPa and at most 1500 MPa. A process for producing the cover glass is provided that includes producing a silica based green glass, hot shaping the silica based green glass, thermally treating the silica based green glass with a nucleation step and a ceramization step, and performing an ion exchange at an exchange bath temperature for a duration of time in an exchange bath.Type: ApplicationFiled: December 12, 2022Publication date: June 15, 2023Applicants: SCHOTT AG, SCHOTT Technical Glass Solutions GmbHInventors: Lars Mueller, Ruediger Dietrich, Thomas Pfeiffer, Julian Koch, Bernd Ruedinger, Meike Schneider, Jochen Alkemper
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Publication number: 20230183128Abstract: A cover glass is provided that includes a silica based glass ceramic with a thickness between 0.4 mm and 0.85 mm. The glass ceramic has a transmittance of more than 80% from 380 nm to 780 nm and a stress attribute selected from: an overall compressive stress (CS) of at least 250 MPa and at most 1500 MPa, a compressive stress at a depth of 30 ?m (CS30) from one of the two faces of at least 160 MPa and at most 525 MPa, a depth of the compression layer (DoCL) of at least 0.2 times the thickness and less than 0.5 times the thickness, and any combinations thereof. The glass ceramic has at least one silica based crystal phase having in a near-surface layer a unit cell volume of at least 1% by volume larger than that of a core where the crystal phase has minimum stresses.Type: ApplicationFiled: December 12, 2022Publication date: June 15, 2023Applicants: SCHOTT AG, SCHOTT Technical Glass Solutions GmbHInventors: Ruediger Dietrich, Meike SCHNEIDER, Jochen Alkemper, Lars Mueller, Thomas Pfeiffer, Julian Koch, Bernd Ruedinger
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Patent number: 11664307Abstract: A multi-voltage domain device includes a semiconductor layer including a first main surface, a second main surface arranged opposite to the first main surface, a first region including first circuity that operates in a first voltage domain, a second region including second circuity that operates in a second voltage domain different than the first voltage domain, and an isolation region that electrically isolates the first region from the second region in a lateral direction that extends parallel to the first and the second main surfaces. The isolation region includes at least one deep trench isolation barrier, each of which extends vertically from the first main surface to the second main surface. The multi-voltage domain device further includes at least one first capacitor configured to generate an electric field laterally across the isolation region between the first region and the second region.Type: GrantFiled: November 3, 2021Date of Patent: May 30, 2023Assignee: Infineon Technologies Austria AGInventors: Lars Mueller-Meskamp, Berthold Astegher, Hermann Gruber, Thomas Christian Neidhart
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Publication number: 20220378910Abstract: The present disclosure provides methods for inducing neoepitope-specific CD8+ T cells in an individual or for inducing trafficking of neoepitope-specific CD8+ T cells to a tumor in an individual using an RNA vaccine or using an RNA vaccine in combination with a PD-1 axis binding antagonist. Also provided herein are PD-1 axis binding antagonists and RNA vaccines that include one or more polynucleotides encoding one or more neoepitopes resulting from cancer-specific somatic mutations present in a tumor specimen obtained from the individual for use in methods of inducing neoepitope-specific CD8+ T cells in an individual or for inducing trafficking of neoepitope-specific CD8+ T cells to a tumor in an individual.Type: ApplicationFiled: June 30, 2022Publication date: December 1, 2022Applicants: Genentech, Inc., BioNTech SE, Hoffmann-La Roche Inc.Inventors: Lars MUELLER, Rachel Lubong SABADO, Mahesh YADAV, Jingbin ZHANG, Ugur SAHIN
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Publication number: 20220349971Abstract: A method for multi-dimensional, relaxation-diffusion magnetic resonance fingerprinting (MRF) includes performing, using a magnetic resonance imaging (MRI) system, a pulse sequence that integrates free-waveform b-tensor diffusion encoding into a magnet resonance fingerprinting pulse sequence to perform a multi-dimensional, relaxation-diffusion encoding while acquiring MRF signal evolutions, processing, using a processor, the acquired MRF signal evolutions to determine at least one relaxation parameter and at least one diffusivity parameter, and generating, using the processor, a report including at least one of the at least one relaxation parameter and the at least diffusivity parameter.Type: ApplicationFiled: May 2, 2022Publication date: November 3, 2022Inventors: Dan Ma, Mark A. Griswold, Derek Jones, Maryam Afzall, Lars Mueller
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Patent number: 11398555Abstract: One illustrative device disclosed herein includes a gate structure positioned above an active semiconductor layer of an SOI substrate and a counter-doped back-gate region positioned in the doped base semiconductor substrate of the SOI substrate. In this particular embodiment, the device also includes a counter-doped back-gate contact region positioned in the base semiconductor substrate, wherein the counter-doped back-gate region and the counter-doped back-gate contact region are doped with a dopant type that is opposite the dopant type in the base semiconductor substrate. In this illustrative example, the counter-doped back-gate region and the counter-doped back-gate contact region are laterally separated from one another by a portion of the doped base semiconductor substrate. The device also includes a conductive back-gate contact structure that is conductively coupled to the counter-doped back-gate contact region.Type: GrantFiled: August 8, 2019Date of Patent: July 26, 2022Assignee: GLOBALFOUNDRIES U.S. INC.Inventors: Lars Mueller-Meskamp, Luca Pirro
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Patent number: 11355719Abstract: An optoelectronic component on a substrate includes a first and a second electrode. The first electrode is arranged on the substrate and the second electrode forms a counter electrode. At least one photoactive layer system is arranged between these electrodes. The at least one photoactive layer system including at least one donor-acceptor system having organic materials.Type: GrantFiled: July 2, 2013Date of Patent: June 7, 2022Assignee: HELIATEK GMBHInventors: Martin Pfeiffer, Christian Uhrich, Ulrike Bewersdorff-Sarlette, Jan Meiss, Karl Leo, Moritz Riede, Sylvio Schubert, Lars Mueller-Meskamp
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Publication number: 20220059453Abstract: A multi-voltage domain device includes a semiconductor layer including a first main surface, a second main surface arranged opposite to the first main surface, a first region including first circuity that operates in a first voltage domain, a second region including second circuity that operates in a second voltage domain different than the first voltage domain, and an isolation region that electrically isolates the first region from the second region in a lateral direction that extends parallel to the first and the second main surfaces. The isolation region includes at least one deep trench isolation barrier, each of which extends vertically from the first main surface to the second main surface. The multi-voltage domain device further includes at least one first capacitor configured to generate an electric field laterally across the isolation region between the first region and the second region.Type: ApplicationFiled: November 3, 2021Publication date: February 24, 2022Applicant: Infineon Technologies Austria AGInventors: Lars MUELLER-MESKAMP, Berthold ASTEGHER, Hermann GRUBER, Thomas Christian NEIDHART
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Patent number: 11183452Abstract: A multi-voltage domain device includes a semiconductor layer including a first main surface, a second main surface arranged opposite to the first main surface, a first region including first circuitry that operates in a first voltage domain, a second region including second circuitry that operates in a second voltage domain different than the first voltage domain, and an isolation region that electrically isolates the first region from the second region in a lateral direction that extends parallel to the first and the second main surfaces. The isolation region includes at least one deep trench isolation barrier, each of which extends vertically from the first main surface to the second main surface. The multi-voltage domain device further includes at least one first capacitor configured to generate an electric field laterally across the isolation region between the first region and the second region.Type: GrantFiled: August 12, 2020Date of Patent: November 23, 2021Inventors: Lars Mueller-Meskamp, Berthold Astegher, Hermann Gruber, Thomas Christian Neidhart
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Publication number: 20210346485Abstract: The present disclosure provides methods, uses, and kits for treating cancer in an individual. The methods comprise administering to the individual a PD-1 axis binding antagonist (such as an anti-PD-1 or anti-PD-L1 antibody) and an RNA vaccine (e.g., a personalized cancer vaccine that comprises one or more polynucleotides encoding one or more neoepitopes resulting from cancer-specific somatic mutations present in a tumor specimen obtained from the individual). Further provided herein are RNA molecules (e.g., a personalized RNA cancer vaccine that comprises one or more polynucleotides encoding one or more neoepitopes resulting from cancer-specific somatic mutations present in a tumor specimen obtained from the individual), as well as DNA molecules and methods useful for production or use of RNA vaccines.Type: ApplicationFiled: July 12, 2021Publication date: November 11, 2021Applicants: Genentech, Inc., BioNTech SEInventors: Lars MUELLER, Gregg Daniel FINE
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Publication number: 20210043733Abstract: One illustrative device disclosed herein includes a gate structure positioned above an active semiconductor layer of an SOI substrate and a counter-doped back-gate region positioned in the doped base semiconductor substrate of the SOI substrate. In this particular embodiment, the device also includes a counter-doped back-gate contact region positioned in the base semiconductor substrate, wherein the counter-doped back-gate region and the counter-doped back-gate contact region are doped with a dopant type that is opposite the dopant type in the base semiconductor substrate. In this illustrative example, the counter-doped back-gate region and the counter-doped back-gate contact region are laterally separated from one another by a portion of the doped base semiconductor substrate. The device also includes a conductive back-gate contact structure that is conductively coupled to the counter-doped back-gate contact region.Type: ApplicationFiled: August 8, 2019Publication date: February 11, 2021Inventors: Lars Mueller-Meskamp, Luca Pirro