Abstract: A cover glass is provided that includes a silica based glass ceramic with a thickness between 0.4 mm and 0.85 mm. The glass ceramic has a transmittance of more than 80% from 380 nm to 780 nm and a stress attribute selected from: an overall compressive stress (CS) of at least 250 MPa and at most 1500 MPa, a compressive stress at a depth of 30 ?m (CS30) from one of the two faces of at least 160 MPa and at most 525 MPa, a depth of the compression layer (DoCL) of at least 0.2 times the thickness and less than 0.5 times the thickness, and any combinations thereof. The glass ceramic has at least one silica based crystal phase having in a near-surface layer a unit cell volume of at least 1% by volume larger than that of a core where the crystal phase has minimum stresses.

Abstract: A lateral high voltage semiconductor device includes a semiconductor substrate with a frontside and a semiconductor element. The semiconductor element includes: a first semiconductor region of a first conductivity type formed within the semiconductor substrate; a second semiconductor region formed within the semiconductor substrate and spaced apart from the first semiconductor region in a first lateral direction parallel to the frontside; and an extension region adjoining the second semiconductor region. The semiconductor device is configured to control a load current between the first and second semiconductor regions. The extension region extends along the frontside of the semiconductor substrate and includes at least one mesa protruding at the frontside of the semiconductor substrate.

Abstract: A semiconductor device includes: a silicon layer having a thickness in a range of 2 ?m to 200 ?m between a frontside and a backside of the silicon layer; a first device region and a second device region laterally isolated from one another in the silicon layer by an isolation structure that extends from the frontside to the backside of the silicon layer; a first insulation layer on the frontside of the silicon layer; a first patterned metallization on the first insulation layer; a second insulation layer on the backside of the silicon layer; and a second patterned metallization on the second insulation layer. The first patterned metallization provides lateral electrical routing along the frontside of the silicon layer. The second patterned metallization provides lateral electrical routing along the backside of the silicon layer. Additional embodiments of semiconductor devices and methods of producing the semiconductor devices are also described.

Abstract: A multi-voltage domain device includes a semiconductor layer including a first main surface, a second main surface arranged opposite to the first main surface, a first region including first circuitry that operates in a first voltage domain, a second region including second circuitry that operates in a second voltage domain different than the first voltage domain, and an isolation region that electrically isolates the first region from the second region in a lateral direction that extends parallel to the first and the second main surfaces. The isolation region includes at least one deep trench isolation barrier, each of which extends vertically from the first main surface to the second main surface. The multi-voltage domain device further includes at least one first capacitor configured to generate an electric field laterally across the isolation region between the first region and the second region.

Abstract: Systems and methods are provided for determining patterns, trends, anomalies, and/or abnormalities in data relating to operation of an insulin delivery pump and user outcomes relating to an insulin delivery pump and determining certain actions and/or operational adjustments to improve the user outcomes, such as blood glucose levels. For example, troubleshooting actions may be recommended upon determining a pattern, trend, abnormality, and/or anomaly in blood glucose levels that is undesirable. In another example, operation of the insulin delivery pump may be adjusted based habits and/or behaviors of the user. For example, insulin delivery timing may be adjusted based on exercise, activity and/or eating patterns. Based on the detected patterns, trends, anomalies, and/or abnormalities, a user device such as a mobile phone or smart device may present prompts for more information, alerts, status updates, and other information intended to improve the user experience.

Abstract: A chemically tempered glass or glass-ceramic article in pane form for use as a cover pane includes a glass or glass-ceramic having a composition comprising the components SiO2, Al2O3, Li2O and Na2O, having a thickness d of 300 ?m to 1000 ?m, a compressive strength at a distance of 30 ?m from a surface of a main face CS30 of at least 60 MPa, and a compressive strength at a distance of 50 ?m from the surface of a main face CS50. The compressive strengths CS30 and CS50 of the same main face are in the following ratio V to one another: V = CS 30 CS 50 ? - 0.0006 * d + 2 , where d is the thickness of the article in ?m.

Abstract: A semiconductor device includes: a semiconductor substrate having a first main surface and a second main surface opposite the first main surface; and a trench structure extending into the semiconductor substrate from the first main surface. The trench structure includes: an upper section extending into the semiconductor substrate from the first main surface; a lower section at an opposite end of the trench structure as the upper section; a first intermediary section between the upper section and the lower section; a field plate in the upper section and dielectrically insulated from the semiconductor substrate; and a first dielectric material completely filling the lower section. The lower section, the upper section, and the first intermediary section have different geometries and/or different dielectric materials. Methods of producing the semiconductor device are also described.

Abstract: A semiconductor device includes: a silicon layer having an electrically insulated backside and a thickness in a range of 10 ?m to 200 ?m between a frontside of the silicon layer and the electrically insulated backside; a high voltage region and a low voltage region formed in the silicon layer and laterally spaced apart from one another; and a first field plate structure extending from the frontside into the silicon layer. The first field plate structure includes a field plate laterally separated from the silicon layer by a dielectric material and/or a pn junction.

Abstract: A semiconductor device includes: a silicon layer having a frontside and an electrically insulated backside; a first trench extending through the silicon layer from the frontside to the electrically insulated backside and laterally isolating a first region of the silicon layer; an electrically conductive material in the first trench; a dielectric material separating the electrically conductive material from silicon material of the silicon layer; and a plurality of silicon plugs laterally surrounded by the dielectric material and dividing the electrically conductive material into a plurality of separate segments in the first trench. Additional embodiments of semiconductor devices and methods for manufacturing the semiconductor devices are also described.

Abstract: A semiconductor die includes: a semiconductor substrate; a transmitter or receiver circuit in the semiconductor substrate; a multi-layer stack on the semiconductor substrate, the multi-layer stack including a plurality of metallization layers separated from one another by an interlayer dielectric; and a transformer in the multi-layer stack and electrically coupled to the transmitter or receiver circuit. The transformer includes a first winding formed in a first metallization layer of the plurality of metallization layers and a second winding formed in a second metallization layer of the plurality of metallization layers. The first winding and the second winding are inductively coupled to one another. A magnetic material in the multi-layer stack is adjacent to at least part of the transformer.

Abstract: A panel-shaped glass element is provided that includes vitreous material having a thermal expansion coefficient of less than 10×10-6 K-1 as well as two opposing surfaces. The glass element furthermore has at least one recess which runs through the glass of the glass element and has a recess wall which runs around the recess and adjoins the two opposing surfaces. The recess wall has a structure with a multiplicity of mutually adjacent rounded dome-shaped depressions. A roughness of the recess wall is formed by these depressions as well as the ridges enclosing the depressions. The recess wall has a mean roughness value (Ra) which is less than 5 µm.

Abstract: A method for multi-dimensional, relaxation-diffusion magnetic resonance fingerprinting (MRF) includes performing, using a magnetic resonance imaging (MRI) system, a pulse sequence that integrates free-waveform b-tensor diffusion encoding into a magnet resonance fingerprinting pulse sequence to perform a multi-dimensional, relaxation-diffusion encoding while acquiring MRF signal evolutions, processing, using a processor, the acquired MRF signal evolutions to determine at least one relaxation parameter and at least one diffusivity parameter, and generating, using the processor, a report including at least one of the at least one relaxation parameter and the at least diffusivity parameter.

Abstract: A semiconductor device includes a semiconductor layer, an electronic element and laterally separated trench isolation structures. The semiconductor layer includes an element region having an inner region, an outer region on opposite sides of the inner region, and a transition region that laterally separates the inner region and the outer region. The electronic element includes a first doped region formed in the inner region and a second doped region formed in the outer region. The trench isolation structures are formed at least in the transition region. Each trench isolation structure extends from a first surface of the semiconductor layer into the semiconductor layer.

Abstract: A multi-voltage domain device includes a semiconductor layer including a first main surface, a second main surface arranged opposite to the first main surface, a first region including first circuitry that operates in a first voltage domain, a second region including second circuitry that operates in a second voltage domain different than the first voltage domain, and an isolation region that electrically isolates the first region from the second region in a lateral direction that extends parallel to the first and the second main surfaces. The isolation region includes at least one deep trench isolation barrier, each of which extends vertically from the first main surface to the second main surface. The multi-voltage domain device further includes at least one first capacitor configured to generate an electric field laterally across the isolation region between the first region and the second region.

Abstract: A cover glass is provided that includes a silica based glass ceramic with a thickness between 0.4 mm and 0.85 mm. The glass ceramic has a transmittance of more than 80% from 380 nm to 780 nm and a stress attribute selected from: an overall compressive stress (CS) of at least 250 MPa and at most 1500 MPa, a compressive stress at a depth of 30 ?m (CS30) from one of the two faces of at least 160 MPa and at most 525 MPa, a depth of the compression layer (DoCL) of at least 0.2 times the thickness and less than 0.5 times the thickness, and any combinations thereof. The glass ceramic has at least one silica based crystal phase having in a near-surface layer a unit cell volume of at least 1% by volume larger than that of a core where the crystal phase has minimum stresses.

Abstract: A cover glass made of a glass ceramic that is silica based and has a main crystal phase of high quartz solid solution or keatite solid solution is provided. The cover glass has a stress profile with at least one inflection point at a depth of the cover glass of more than 10 ?m, a thickness from 0.1 mm to 2 mm, and a chemical tempering structure with a surface compressive stress of at least 250 MPa and at most 1500 MPa. A process for producing the cover glass is provided that includes producing a silica based green glass, hot shaping the silica based green glass, thermally treating the silica based green glass with a nucleation step and a ceramization step, and performing an ion exchange at an exchange bath temperature for a duration of time in an exchange bath.

Abstract: A multi-voltage domain device includes a semiconductor layer including a first main surface, a second main surface arranged opposite to the first main surface, a first region including first circuity that operates in a first voltage domain, a second region including second circuity that operates in a second voltage domain different than the first voltage domain, and an isolation region that electrically isolates the first region from the second region in a lateral direction that extends parallel to the first and the second main surfaces. The isolation region includes at least one deep trench isolation barrier, each of which extends vertically from the first main surface to the second main surface. The multi-voltage domain device further includes at least one first capacitor configured to generate an electric field laterally across the isolation region between the first region and the second region.

Abstract: A semiconductor device includes a semiconductor layer with an inner portion, an outer portion laterally surrounding the inner portion, and a transition portion laterally surrounding the inner portion and separating the inner portion and the outer portion. A first electric element includes a first doped region formed in the inner portion and a second doped region formed in the outer portion. The first electric element is configured to at least temporarily block a voltage applied between the first doped region and the second doped region. A trench isolation structure extends from a first surface into the semiconductor layer and segments at least one of the inner portion, the transition portion, and the outer portion.

Abstract: A spacer wafer for producing spacers of electro-optical converter housings is provided. The spacer wafer is a transparent glass plate having a multiplicity of openings separated from one another and distributed in a grid so that singulated spacers are obtainable by severing sections of the glass plate along separating lines between the openings. The openings have side walls with microstructuring that has a roughness with an average roughness value Ra of less than 0.5 ?m with a measurement distance of 500 ?m.

Abstract: A method for peeling potatoes with a food processor and a food processor which comprises for food preparation a detachable food preparation vessel, a heating element for heating a food in the food preparation vessel and a rotatable tool for mixing or chopping the food in the food preparation vessel. The method includes attaching a potato peeling disc having an abrasive structure on its surface from above to the tool which is located centrally at a bottom of the food preparation vessel to establish a manually releasable, rotationally coupled connection such that in operation the potato peeling disc rotates at the same rotational speed as the tool; addition of potatoes into the food preparation vessel from above onto the potato peeling disc; motorized rotation of the tool in a first direction of rotation and peeling of the potatoes with the potato peeling disc inside the food preparation vessel.