Abstract: A multi-voltage domain device includes a semiconductor layer including a first main surface, a second main surface arranged opposite to the first main surface, a first region including first circuitry that operates in a first voltage domain, a second region including second circuitry that operates in a second voltage domain different than the first voltage domain, and an isolation region that electrically isolates the first region from the second region in a lateral direction that extends parallel to the first and the second main surfaces. The isolation region includes at least one deep trench isolation barrier, each of which extends vertically from the first main surface to the second main surface. The multi-voltage domain device further includes at least one first capacitor configured to generate an electric field laterally across the isolation region between the first region and the second region.

Abstract: A semiconductor device includes: a semiconductor substrate having a first main surface and a second main surface opposite the first main surface; and a trench structure extending into the semiconductor substrate from the first main surface. The trench structure includes: an upper section extending into the semiconductor substrate from the first main surface; a lower section at an opposite end of the trench structure as the upper section; a first intermediary section between the upper section and the lower section; a field plate in the upper section and dielectrically insulated from the semiconductor substrate; and a first dielectric material completely filling the lower section. The lower section, the upper section, and the first intermediary section have different geometries and/or different dielectric materials. Methods of producing the semiconductor device are also described.

Abstract: A semiconductor device includes: a silicon layer having an electrically insulated backside and a thickness in a range of 10 ?m to 200 ?m between a frontside of the silicon layer and the electrically insulated backside; a high voltage region and a low voltage region formed in the silicon layer and laterally spaced apart from one another; and a first field plate structure extending from the frontside into the silicon layer. The first field plate structure includes a field plate laterally separated from the silicon layer by a dielectric material and/or a pn junction.

Abstract: A semiconductor device includes: a silicon layer having a frontside and an electrically insulated backside; a first trench extending through the silicon layer from the frontside to the electrically insulated backside and laterally isolating a first region of the silicon layer; an electrically conductive material in the first trench; a dielectric material separating the electrically conductive material from silicon material of the silicon layer; and a plurality of silicon plugs laterally surrounded by the dielectric material and dividing the electrically conductive material into a plurality of separate segments in the first trench. Additional embodiments of semiconductor devices and methods for manufacturing the semiconductor devices are also described.

Abstract: A semiconductor die includes: a semiconductor substrate; a transmitter or receiver circuit in the semiconductor substrate; a multi-layer stack on the semiconductor substrate, the multi-layer stack including a plurality of metallization layers separated from one another by an interlayer dielectric; and a transformer in the multi-layer stack and electrically coupled to the transmitter or receiver circuit. The transformer includes a first winding formed in a first metallization layer of the plurality of metallization layers and a second winding formed in a second metallization layer of the plurality of metallization layers. The first winding and the second winding are inductively coupled to one another. A magnetic material in the multi-layer stack is adjacent to at least part of the transformer.

Abstract: A multi-voltage domain device includes a semiconductor layer including a first main surface, a second main surface arranged opposite to the first main surface, a first region including first circuitry that operates in a first voltage domain, a second region including second circuitry that operates in a second voltage domain different than the first voltage domain, and an isolation region that electrically isolates the first region from the second region in a lateral direction that extends parallel to the first and the second main surfaces. The isolation region includes at least one deep trench isolation barrier, each of which extends vertically from the first main surface to the second main surface. The multi-voltage domain device further includes at least one first capacitor configured to generate an electric field laterally across the isolation region between the first region and the second region.

Abstract: A multi-voltage domain device includes a semiconductor layer including a first main surface, a second main surface arranged opposite to the first main surface, a first region including first circuity that operates in a first voltage domain, a second region including second circuity that operates in a second voltage domain different than the first voltage domain, and an isolation region that electrically isolates the first region from the second region in a lateral direction that extends parallel to the first and the second main surfaces. The isolation region includes at least one deep trench isolation barrier, each of which extends vertically from the first main surface to the second main surface. The multi-voltage domain device further includes at least one first capacitor configured to generate an electric field laterally across the isolation region between the first region and the second region.

Abstract: One illustrative device disclosed herein includes a gate structure positioned above an active semiconductor layer of an SOI substrate and a counter-doped back-gate region positioned in the doped base semiconductor substrate of the SOI substrate. In this particular embodiment, the device also includes a counter-doped back-gate contact region positioned in the base semiconductor substrate, wherein the counter-doped back-gate region and the counter-doped back-gate contact region are doped with a dopant type that is opposite the dopant type in the base semiconductor substrate. In this illustrative example, the counter-doped back-gate region and the counter-doped back-gate contact region are laterally separated from one another by a portion of the doped base semiconductor substrate. The device also includes a conductive back-gate contact structure that is conductively coupled to the counter-doped back-gate contact region.

Abstract: An optoelectronic component on a substrate includes a first and a second electrode. The first electrode is arranged on the substrate and the second electrode forms a counter electrode. At least one photoactive layer system is arranged between these electrodes. The at least one photoactive layer system including at least one donor-acceptor system having organic materials.

Abstract: A multi-voltage domain device includes a semiconductor layer including a first main surface, a second main surface arranged opposite to the first main surface, a first region including first circuity that operates in a first voltage domain, a second region including second circuity that operates in a second voltage domain different than the first voltage domain, and an isolation region that electrically isolates the first region from the second region in a lateral direction that extends parallel to the first and the second main surfaces. The isolation region includes at least one deep trench isolation barrier, each of which extends vertically from the first main surface to the second main surface. The multi-voltage domain device further includes at least one first capacitor configured to generate an electric field laterally across the isolation region between the first region and the second region.

Abstract: A multi-voltage domain device includes a semiconductor layer including a first main surface, a second main surface arranged opposite to the first main surface, a first region including first circuitry that operates in a first voltage domain, a second region including second circuitry that operates in a second voltage domain different than the first voltage domain, and an isolation region that electrically isolates the first region from the second region in a lateral direction that extends parallel to the first and the second main surfaces. The isolation region includes at least one deep trench isolation barrier, each of which extends vertically from the first main surface to the second main surface. The multi-voltage domain device further includes at least one first capacitor configured to generate an electric field laterally across the isolation region between the first region and the second region.

Abstract: One illustrative device disclosed herein includes a gate structure positioned above an active semiconductor layer of an SOI substrate and a counter-doped back-gate region positioned in the doped base semiconductor substrate of the SOI substrate. In this particular embodiment, the device also includes a counter-doped back-gate contact region positioned in the base semiconductor substrate, wherein the counter-doped back-gate region and the counter-doped back-gate contact region are doped with a dopant type that is opposite the dopant type in the base semiconductor substrate. In this illustrative example, the counter-doped back-gate region and the counter-doped back-gate contact region are laterally separated from one another by a portion of the doped base semiconductor substrate. The device also includes a conductive back-gate contact structure that is conductively coupled to the counter-doped back-gate contact region.

Abstract: In sophisticated semiconductor devices, the lateral electric field in fully depleted transistor elements operated at elevated supply voltages may be significantly reduced by establishing a laterally graded dopant profile at edge regions of the respective channel regions. In some illustrative embodiments to this end, one or more dopant species may be incorporated prior to completing the gate electrode structure.

Abstract: In semiconductor devices, high-k dielectric materials may be formed on the basis of engineered surface conditions, thereby contributing to superior uniformity of the resulting characteristics. In some illustrative embodiments, the dielectric material may be stabilized in a ferroelectric phase, wherein the previous surface modulation, which, in the illustrative embodiments may include the introduction of respective species, such as dopant species, thereby contributing to uniform ferroelectric characteristics. In some illustrative embodiments, the process strategy may be applied to a buried insulating layer of an SOI substrate.

Abstract: In sophisticated semiconductor devices, the lateral electric field in fully depleted transistor elements operated at elevated supply voltages may be significantly reduced by establishing a laterally graded dopant profile at edge regions of the respective channel regions. In some illustrative embodiments to this end, one or more dopant species may be incorporated prior to completing the gate electrode structure.

Abstract: In semiconductor devices, high-k dielectric materials may be formed on the basis of engineered surface conditions, thereby contributing to superior uniformity of the resulting characteristics. In some illustrative embodiments, the dielectric material may be stabilized in a ferroelectric phase, wherein the previous surface modulation, which, in the illustrative embodiments may include the introduction of respective species, such as dopant species, thereby contributing to uniform ferroelectric characteristics. In some illustrative embodiments, the process strategy may be applied to a buried insulating layer of an SOI substrate.

Abstract: What is presented here is a transparent electrode having: at least one carrier layer for stabilizing the electrode; at least one electrically conductive layer containing metal nanowires, which is produced by spreading a suspension of a liquid and the metal nanowires surrounded by a stabilizing layer, along the carrier layer and drying same by removing the liquid; and at least one functional organic layer formed along the carrier layer, which, while the electrically conductive layer dries, by an electrical interaction with the metal nanowires and/or with the stabilizing layers of the metal nanowires, changes an interaction between the metal nanowires and the stabilizing layers such that the result is a substance-to-substance bond between the metal nanowires.

Abstract: The invention relates to a method for producing an electrode layer of an electrical device, wherein the method includes the following steps: providing a quantity of nanoparticles from an electrically conductive material, the surfaces of each of which have a layer of a hygroscopic stabilizer material, preparing a substrate and producing an electrode layer on a substrate surface, wherein the nanoparticles in this context are deposited on the substrate surface and are tempered in a solvent atmosphere of a polar solvent.

Abstract: What is presented here is a transparent electrode having: at least one carrier layer for stabilizing the electrode; at least one electrically conductive layer containing metal nanowires, which is produced by spreading a suspension of a liquid and the metal nanowires surrounded by a stabilizing layer, along the carrier layer and drying same by removing the liquid; and at least one functional organic layer formed along the carrier layer, which, while the electrically conductive layer dries, by an electrical interaction with the metal nanowires and/or with the stabilizing layers of the metal nanowires, changes an interaction between the metal nanowires and the stabilizing layers such that the result is a substance-to-substance bond between the metal nanowires.

Abstract: The invention relates to a method for producing an electrode layer of an electrical device, wherein the method includes the following steps: providing a quantity of nanoparticles from an electrically conductive material, the surfaces of each of which have a layer of a hygroscopic stabiliser material, preparing a substrate and producing an electrode layer on a substrate surface, wherein the nanoparticles in this context are deposited on the substrate surface and are tempered in a solvent atmosphere of a polar solvent.