Abstract: A system and method of preventing metastability in conjunction with the receipt in a first clock domain of an asynchronous digital signal from a second clock domain when the first domain operates with a first clock frequency, and the second domain operates with a second clock frequency that is known within the first domain. The first domain sends information to the second domain, and includes a reference signal containing phase information known in the first domain. The information is clocked into the second domain utilizing the reference information. The second domain then sends the asynchronous digital signal to the first clock domain. A receiving unit in the first domain determines the phase information from the received signal with a known degree of maximum uncertainty that is less than one period of the reference signal. The first domain then stably reads the received asynchronous digital signal.

Abstract: A pulse detector detects if a clock pulse signal is in phase with a reference clock pulse signal in an efficient manner with very high accuracy. The pulse detector includes a first delay unit adapted to receive an input clock pulse signal and to delay the input clock pulse signal by a first pre-specified delay for output as output clock pulse signal, and a second delay unit adapted to delay the output clock pulse signal by a second pre-specified delay. A sampling unit is adapted to sample the input clock pulse signal and the output of the second delay unit at a sampling time defined by a reference clock pulse signal and to output the samples for phase delay indication.

Abstract: A fault tolerant processing system includes at least two processing planes. Each processing plane processes an input signal and generates an output signal. The system further includes plane termination logic for receiving the output signals of the processing planes to generate a non-redundant output signal. Each processing plane is provided with devices for detecting a fault in the plane, and devices for substituting, in response to detection of a fault in the plane, a signal component, referred to as control component, representing a predetermined logical state for each one of those components of the processed input signal that are affected by the detected fault. Furthermore, the plane termination logic includes devices for performing logical operations on the output signals of the planes such that, in the generation of the non-redundant output signal, unaffected signal components of a received signal override corresponding control components of another received signal.

Abstract: To detect if a clock pulse signal is in phase with a reference clock pulse signal in an efficient manner with very high accuracy there is proposed a pulse detector, comprising a first delay unit (12) adapted to receive an input clock pulse signal (&phgr;(t)) and to delay the input clock pulse signal (&phgr;(t)) by a first pre-specified delay (d1) for output as output clock pulse signal (&phgr;out(t)) and a second delay unit (14) adapted to delay the output clock pulse signal (&phgr;out(t)) by a second pre-specified delay (d2). A sampling unit (16) is adapted to sample the input clock pulse signal (&phgr;(t)) and the output of the second delay unit (14) (&phgr;out(t−d1−d2)) at a sampling time defined by a reference clock pulse signal (&phgr;R(t)) and to output the samples (v1, v2) for phase delay indication.

Abstract: A plurality of input signals are switched in an apparatus including redundant switching planes and hardware for receiving an output signal from each of the redundant switching planes. Each switching plane is for switching the plurality of input signals, and each switching plane includes at least two switching modules, each switching module being connected to receive a subset of the input signals directly from an input signal source coupled to the apparatus. Each switching module is further connected to receive a remaining subset of the input signals from remaining switching modules on the same switching plane; and each switching module generates an output signal having components selected from the plurality of input signals. To improve performance in the event of a double fault, each switching module detects whether any of the remaining switching modules on the same switching plane are faulty.