Abstract: A system including a receiver and a processing pipeline. The receiver is configured to generate a data block by encapsulating a data packet in a header portion and a tail portion that do not include valid information bits. The processing pipeline is configured to, in a first processing stage, store the data block, and store, separately from the data block, additional information associated with the data block. The processing pipeline is further configured to, without modifying a length of the data block, either add bits to the header portion or the tail portion to increase the length of the data packet or subtract bits from the data packet to decrease the length of the data packet, and modify the additional information in accordance with the bits added to the header portion or the tail portion or the bits subtracted from the data packet.

Abstract: A pipeline of memory banks is configured to store and retrieve a forwarding address by distributing portions of the address across the memory banks and subsequently searching for the distributed values. A first value of the address is recoverable by searching for a value, stored by a first memory bank, by consuming a predetermined number of bits of a data unit from a data packet. If present, a subsequent value of the address is recoverable by searching another memory bank of the pipeline for a value of the address contained by a node of a linked list. The pipeline recovers the address by combining value found at the first memory bank with the value found by the node of the linked list at the other memory bank.

Abstract: A system including a receiver and a processing pipeline. The receiver is configured to generate a data block by encapsulating a data packet in a header portion and a tail portion that do not include valid information bits. The processing pipeline is configured to, in a first processing stage, store the data block, and store, separately from the data block, additional information associated with the data block. The processing pipeline is further configured to, without modifying a length of the data block, either add bits to the header portion or the tail portion to increase the length of the data packet or subtract bits from the data packet to decrease the length of the data packet, and modify the additional information in accordance with the bits added to the header portion or the tail portion or the bits subtracted from the data packet.

Abstract: The present invention relates to a method and apparatus for pipelined processing of data packets. A pipeline in a processor comprises an access point providing simultaneous access to one or more devices, said devices mainly for data processing operations not provided by the pipeline. The access point comprises at least one FIFO store for storing data entering the access point, a response FIFO store for storing responses received from the device(s), and a synchronization mechanism adapted to synchronize the fetching of the first entry in the FIFO store(s) and the first entry in the response FIFO store. The synchronization mechanism could advantageously be a fixed time delay mechanism. When the fixed time initiated by the fixed time delay mechanism has elapsed, the first response in the response FIFO store is merged into the data stored in the first entry in the FIFO store(s) for storing data entering the access point.

Abstract: A processor is presented, comprising a programmable pipeline and at least one interface engine (130), adapted to be connected to at least one external device (140) located externally of the processor. The processor is characterized in that the interface engine (130) is adapted to receive a request (170) from the programmable pipeline, to send to the external device (140) a request output (270), based on the request (170), and to send to the pipeline a response (340) to the request (170). Preferably, the request (170) comprises a first request code (210), according to a first coding scheme, and the interface engine (130) is adapted to execute a program, the execution being dependent upon the first request code, to obtain a device control code (300) for the external device (140), according to a second coding scheme.

Abstract: The present invention relates to a method and apparatus for pipelined processing of data. When a data packet containing information is received by a processor operating according to pipelined processing, bits are added to the data packet and an intermediate packet, comprising more bits than the received data packet, is generated. To the intermediate packet is associated information reference, the information reference comprising information regarding the length and position of the information in the intermediate packet. As the intermediate packet is processed, changes to the intermediate packet resulting in changes of the length or the position of the information in the intermediate packet will trigger changes of the information reference. When the intermediate packet exits the processor, superfluous bits are removed.

Abstract: The present invention relates to a method and apparatus for pipelined processing of data packets. A pipeline in a processor comprises an access point providing simultaneous access to one or more devices, said devices mainly for data processing operations not provided by the pipeline. The access point comprises at least one FIFO store for storing data entering the access point, a response FIFO store for storing responses received from the device(s), and a synchronisation mechanism adapted to synchronise the fetching of the first entry in the FIFO store(s) and the first entry in the response FIFO store. The synchronisation mechanism could advantageously be a fixed time delay mechanism. When the fixed time initiated by the fixed time delay mechanism has elapsed, the first response in the response FIFO store is merged into the data stored in the first entry in the FIFO store(s) for storing data entering the access point.

Abstract: Disclosed herein are methods and apparatus for operating and deploying a broadband wireless network having at least one data transmission node and a plurality of CPE units, wherein there is a wireless data link at least in part between the data transmission node and the CPE units, and further wherein the management and configuration of the network is managed centrally and at least one of authorization, authentication, data stream prioritization or queuing is accomplished through the operation of the CPE units. According to one embodiment there is provided a user group manager that provides a user interface for at least one local service provider to manage information about end users served by the local service provider. In another embodiment, management and configuration of the network is managed using a device that communicates with CPE units and the data transmission nodes.

Abstract: The invention relates to fast serial-parallel and parallel-serial converters, and in them included frequency dividers. The serial-parallel converter comprises a shift register, an output register and a frequency divider. The parallel-serial converter comprises a register and a frequency divider. All registers and frequency dividers comprise clock inputs, that each is connected to some incoming clock signal. According to the invention, the frequency divider comprises at least two circuits with the function of AND-gates with clocked memory circuits. Each circuit comprises a clock input, a first AND-input, a second AND-input, and at least one output that outputs the value of the logical AND-function of the two AND-inputs. The first AND-inputs are connected to each other and to an inverted signal from one of the outputs. The second AND-inputs except on the first circuit are connected to the output of the preceding circuit. Finally a frequency divided clock signal may be taken out from one of the outputs.