Patents by Inventor Lars Oskar Flordal

Lars Oskar Flordal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10824357
    Abstract: A process of updating data for a block of an array of data elements stored in an allocated memory region for the block comprises reading in data for a first group of the data elements, updating the data for the first group, and then writing back the updated data to memory. The process can avoid overwriting data for a second group of the data elements that is yet to be read in from the memory region by writing back the updated data for the first group starting at a selected memory address, for example other than the start address of the memory region. The data for the second group of data elements can then be read in and updated, and the updated data can be written back to memory. The process can reduce the amount of memory bandwidth and local cache that needs to be used.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: November 3, 2020
    Assignee: Arm Limited
    Inventors: Lars Oskar Flordal, Jian Wang, Jakob Axel Fries
  • Patent number: 10769838
    Abstract: A graphics processing system can divide a render output into plural larger patches, with each larger patch encompassing plural smaller patches. A rasteriser of the system tests a larger patch against a primitive to be processed to determine if the primitive covers the larger patch. When it is determined that the primitive only partially covers the larger patch, the larger patch is sub-divided into plural smaller patches and at least one of the smaller patches is re-tested against the primitive. Conversely, when it is determined that the primitive completely covers the larger patch, the larger patch is output from the rasteriser in respect of the primitive for processing by a subsequent stage, of the graphics processing system. The system can provide efficient, hierarchal, processing of primitives, whilst helping to prevent the output of the rasteriser from becoming blocked.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: September 8, 2020
    Assignee: Arm Limited
    Inventors: Frode Heggelund, Toni Viki Brkic, Christian Vik Grovdal, Lars Oskar Flordal
  • Patent number: 10726610
    Abstract: A graphics processing system maintains a fragment tracking record that stores metadata relating to one or more previously received primitives. The metadata can indicate that the one or more previously received primitives are suitably covered by a subsequently received primitive such that one or more fragment processing operations need not be performed in respect of those one or more previously received primitives. The metadata stored for the one or more previously received primitives can then later be queried by one or more later stages of the graphics processing system to determine whether one or more fragments for the one or more previously received primitives can be at least partially discarded or “killed”.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: July 28, 2020
    Assignee: Arm Limited
    Inventors: Frode Heggelund, Toni Viki Brkic, Christian Vik Grovdal, Lars Oskar Flordal
  • Patent number: 10642343
    Abstract: In a data processing system that includes a graphics processor and a video processor, graphics textures for use by the graphics processor are stored as encoded frames of video data. The video processor then decodes the video frames to reproduce the graphics texture(s) that the video frames encode, and stores the decoded graphics texture or textures in memory for use by the graphics processor. The graphics processor then reads the decoded graphics textures for use when generating its render outputs, such as output frames for display.
    Type: Grant
    Filed: May 9, 2017
    Date of Patent: May 5, 2020
    Assignee: ARM Ltd
    Inventor: Lars Oskar Flordal
  • Publication number: 20200074721
    Abstract: A graphics processing system maintains a fragment tracking record that stores metadata relating to one or more previously received primitives. The metadata can indicate that the one or more previously received primitives are suitably covered by a subsequently received primitive such that one or more fragment processing operations need not be performed in respect of those one or more previously received primitives. The metadata stored for the one or more previously received primitives can then later be queried by one or more later stages of the graphics processing system to determine whether one or more fragments for the one or more previously received primitives can be at least partially discarded or “killed”.
    Type: Application
    Filed: August 29, 2018
    Publication date: March 5, 2020
    Applicant: Arm Limited
    Inventors: Frode Heggelund, Toni Viki Brkic, Christian Vik Grovdal, Lars Oskar Flordal
  • Patent number: 10580113
    Abstract: A tile-based graphics processing system comprises a graphics processing pipeline comprising a plurality of processing stages, including at least a rasteriser that rasterises input primitives to generate graphics fragments to be processed, and a renderer that processes fragments generated by the rasteriser to generate rendered fragment data, and a tile buffer configured to store data locally to the graphics processing pipeline. The graphics processing system is operable to cause data for use when performing graphics processing operations for each tile of a set of plural tiles of a plurality of tiles to be loaded into the tile buffer before causing graphics processing operations to be performed for any of the tiles of the set of plural tiles.
    Type: Grant
    Filed: October 5, 2018
    Date of Patent: March 3, 2020
    Assignee: Arm Limited
    Inventors: Lars Oskar Flordal, Toni Viki Brkic, Christian Vik Grovdal, Andreas Due Engh-Halstvedt, Frode Heggelund
  • Publication number: 20190392546
    Abstract: A data processing system includes a producer processor that produces a sequence of data outputs for use by consumer processors of the data processing system. The system also includes a memory for storing a sequence of data outputs produced by the data processor. The data processor encodes data outputs as encoded blocks of data, storing a particular encoded block of a first frame in a first location in the memory and an indication of the first location. The data processor stores a corresponding encoded block of a second data output in a second location and updates the indication to the second location.
    Type: Application
    Filed: June 17, 2019
    Publication date: December 26, 2019
    Applicant: Arm Limited
    Inventors: Lars Oskar Flordal, Jakob Axel Fries
  • Patent number: 10466915
    Abstract: A method of storing encoded blocks of data in memory comprises generating headers for the encoded blocks of data. The headers are stored in memory according to a tiled layout based on tiles of plural adjacent blocks of data elements of the array of data elements. Respective sets of the encoded blocks of data are also stored in respective distinct regions of memory locations that have been allocated to those sets. The method provides an efficient way to access headers and corresponding encoded blocks of data in memory.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: November 5, 2019
    Assignee: Arm Limited
    Inventors: Quinn Carter, Lars Oskar Flordal, Jakob Axel Fries
  • Patent number: 10430099
    Abstract: A data array to be stored is first divided into a plurality of blocks. Each block is further sub-divided into a set of sub-blocks. Data representing sub-blocks of the data array is stored, together with a header data block for each block that the data array has been divided into. For each block, it is determined whether all the data positions for the block have the same data value associated with them, and, if so, an indication that all of the data positions within the block have the same data value associated with them, and an indication of the same data value that is associated with each of the data positions in the block, is stored in the header data block for that block of the data array.
    Type: Grant
    Filed: March 29, 2017
    Date of Patent: October 1, 2019
    Assignee: Arm Limited
    Inventors: Quinn Carter, Lars Oskar Flordal, Jakob Axel Fries, Andreas Due Engh-Halstvedt
  • Patent number: 10395394
    Abstract: A method of encoding a block of an array of data elements comprises selectively writing out an encoded version of the block either that is encoded using a first encoding scheme, which provides encoded blocks of non-fixed data size, or that is encoded using a second encoding scheme, which provides encoded blocks of fixed data size. The selection of which version of the encoded block to write out is based on the size of the encoded block when encoded using the first encoding scheme. This provides the potential for the encoded block that is written out to be compressed in a more superior manner using the first encoding scheme where possible, while also providing an encoded block that has a predictable maximum compressed size.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: August 27, 2019
    Assignee: Arm Limited
    Inventors: Lars Oskar Flordal, Jakob Axel Fries, Toni Viki Brkic
  • Publication number: 20190188896
    Abstract: A graphics processing system can divide a render output into plural larger patches, with each larger patch encompassing plural smaller patches. A rasteriser of the system tests a larger patch against a primitive to be processed to determine if the primitive covers the larger patch. When it is determined that the primitive only partially covers the larger patch, the larger patch is sub-divided into plural smaller patches and at least one of the smaller patches is re-tested against the primitive. Conversely, when it is determined that the primitive completely covers the larger patch, the larger patch is output from the rasteriser in respect of the primitive for processing by a subsequent stage, of the graphics processing system. The system can provide efficient, hierarchal, processing of primitives, whilst helping to prevent the output of the rasteriser from becoming blocked.
    Type: Application
    Filed: December 13, 2018
    Publication date: June 20, 2019
    Applicant: Arm Limited
    Inventors: Frode Heggelund, Toni Viki Brkic, Christian Vik Grovdal, Lars Oskar Flordal
  • Publication number: 20190108610
    Abstract: A tile-based graphics processing system comprises a graphics processing pipeline comprising a plurality of processing stages, including at least a rasteriser that rasterises input primitives to generate graphics fragments to be processed, and a renderer that processes fragments generated by the rasteriser to generate rendered fragment data, and a tile buffer configured to store data locally to the graphics processing pipeline. The graphics processing system is operable to cause data for use when performing graphics processing operations for each tile of a set of plural tiles of a plurality of tiles to be loaded into the tile buffer before causing graphics processing operations to be performed for any of the tiles of the set of plural tiles.
    Type: Application
    Filed: October 5, 2018
    Publication date: April 11, 2019
    Applicant: Arm Limited
    Inventors: Lars Oskar Flordal, Toni Viki Brkic, Christian Vik Grovdal, Andreas Due Engh-Halstvedt, Frode Heggelund
  • Patent number: 10013790
    Abstract: In a graphics processing system, a driver for the graphics processing pipeline can include conditional graphics processing tasks in the graphics processing tasks that are to be executed by the graphics processing pipeline to generate a render output required by an application. Each such conditional task has associated with it a condition to be used by the graphics processing pipeline to determine whether to execute processing for the task or not and a region of the render output over which the processing for the task will be executed when the condition for the task is met. The graphics processing pipeline determines whether the condition associated with the task has been met, and only executes the processing for the task if the condition associated with the task has been met.
    Type: Grant
    Filed: February 12, 2016
    Date of Patent: July 3, 2018
    Assignee: Arm Limited
    Inventors: Sandeep Kakarlapudi, Andreas Due Engh-Halstvedt, Lars Oskar Flordal, Arne Bergene Fossaa
  • Patent number: 10001941
    Abstract: A tile-based graphics processing pipeline includes rendering circuitry for rendering graphics fragments to generate rendered fragment data. Each graphics fragment has associated with it a set of sampling positions to be rendered. The pipeline also includes a tile buffer configured to store rendered fragment data for sampling positions prior to the rendered fragment data being written out to memory, write out circuitry configured to write a compressed representation of the rendered fragment data for a tile in the tile buffer to memory, and processing circuitry. The processing circuitry identities, based on the writing of rendered fragment data to the tile buffer, any blocks comprising sampling positions within a tile having the same data value associated with each sampling position in the block, and to, when such a block of sampling positions is identified, trigger the write out circuitry to write a compressed representation of the block to the memory.
    Type: Grant
    Filed: March 25, 2017
    Date of Patent: June 19, 2018
    Assignee: Arm Limited
    Inventors: Lars Oskar Flordal, Toni Viki Brkic, Jakob Axel Fries
  • Publication number: 20180129419
    Abstract: A process of updating data for a block of an array of data elements stored in an allocated memory region for the block comprises reading in data for a first group of the data elements, updating the data for the first group, and then writing back the updated data to memory. The process can avoid overwriting data for a second group of the data elements that is yet to be read in from the memory region by writing back the updated data for the first group starting at a selected memory address, for example other than the start address of the memory region. The data for the second group of data elements can then be read in and updated, and the updated data can be written back to memory. The process can reduce the amount of memory bandwidth and local cache that needs to be used.
    Type: Application
    Filed: October 30, 2017
    Publication date: May 10, 2018
    Applicant: Arm Limited
    Inventors: Lars Oskar Flordal, Jian Wang, Jakob Axel Fries
  • Publication number: 20180004443
    Abstract: A method of storing encoded blocks of data in memory comprises generating headers for the encoded blocks of data. The headers are stored in memory according to a tiled layout based on tiles of plural adjacent blocks of data elements of the array of data elements. Respective sets of the encoded blocks of data are also stored in respective distinct regions of memory locations that have been allocated to those sets. The method provides an efficient way to access headers and corresponding encoded blocks of data in memory.
    Type: Application
    Filed: June 28, 2017
    Publication date: January 4, 2018
    Applicant: ARM Limited
    Inventors: Quinn Carter, Lars Oskar Flordal, Jakob Axel Fries
  • Publication number: 20170352165
    Abstract: A method of encoding a block of an array of data elements comprises selectively writing out an encoded version of the block either that is encoded using a first encoding scheme, which provides encoded blocks of non-fixed data size, or that is encoded using a second encoding scheme, which provides encoded blocks of fixed data size. The selection of which version of the encoded block to write out is based on the size of the encoded block when encoded using the first encoding scheme. This provides the potential for the encoded block that is written out to be compressed in a more superior manner using the first encoding scheme where possible, whilst also providing an encoded block that has a predictable maximum compressed size.
    Type: Application
    Filed: May 31, 2017
    Publication date: December 7, 2017
    Applicant: ARM Limited
    Inventors: Lars Oskar Flordal, Jakob Axel Fries, Toni Viki Brkic
  • Publication number: 20170329395
    Abstract: In a data processing system that includes a graphics processor and a video processor, graphics textures for use by the graphics processor are stored as encoded frames of video data. The video processor then decodes the video frames to reproduce the graphics texture(s) that the video frames encode, and stores the decoded graphics texture or textures in memory for use by the graphics processor. The graphics processor then reads the decoded graphics textures for use when generating its render outputs, such as output frames for display.
    Type: Application
    Filed: May 9, 2017
    Publication date: November 16, 2017
    Applicant: ARM Limited
    Inventor: Lars Oskar Flordal
  • Publication number: 20170285955
    Abstract: A data array to be stored is first divided into a plurality of blocks. Each block is further sub-divided into a set of sub-blocks. Data representing sub-blocks of the data array is stored, together with a header data block for each block that the data array has been divided into. For each block, it is determined whether all the data positions for the block have the same data value associated with them, and, if so, an indication that all of the data positions within the block have the same data value associated with them, and an indication of the same data value that is associated with each of the data positions in the block, is stored in the header data block for that block of the data array.
    Type: Application
    Filed: March 29, 2017
    Publication date: October 5, 2017
    Applicant: ARM Limited
    Inventors: Quinn Carter, Lars Oskar Flordal, Jakob Axel Fries, Andreas Due Engh-Halstvedt
  • Publication number: 20170287101
    Abstract: A tile-based graphics processing pipeline includes rendering circuitry for rendering graphics fragments to generate rendered fragment data. Each graphics fragment has associated with it a set of sampling positions to be rendered. The pipeline also includes a tile buffer configured to store rendered fragment data for sampling positions prior to the rendered fragment data being written out to memory, write out circuitry configured to write a compressed representation of the rendered fragment data for a tile in the tile buffer to memory, and processing circuitry. The processing circuitry identities, based on the writing of rendered fragment data to the tile buffer, any blocks comprising sampling positions within a tile having the same data value associated with each sampling position in the block, and to, when such a block of sampling positions is identified, trigger the write out circuitry to write a compressed representation of the block to the memory.
    Type: Application
    Filed: March 25, 2017
    Publication date: October 5, 2017
    Applicant: ARM Limited
    Inventors: Lars Oskar Flordal, Toni Viki Brkic, Jakob Axel Fries