Abstract: A read and notify request is issued by a first processing unit to a lock manager on a different chip. A lock manager determines whether a condition specified by the request in relation to a variable for controlling access to a memory buffer is met. If the two are not equal, a notification request is registered until the variable changes. The second processing unit accesses the memory buffer and, when it has finished, updates the variable. If the variable then satisfies the condition specified by the read and notify request, the first processing unit is then notified by the lock manager and accesses the memory buffer. In this way, the first processing unit does not need to continually poll to determine when the variable has changed, but is notified when it is its turn to access the memory buffer.

Abstract: A multi-tile processing unit in which the tiles in the processing unit may be divided between two or more different external sync groups for performing barrier synchronisations. In this way, different sets of tiles of the same processing unit each sync with different sets of tiles external to that processing unit.

Abstract: The provision of redundancy in a sync network, which protects the sync network against faults, such as broken cables in the sync network. The gateway comprises a sync propagation module configured to provide redundant sync requests that are sent along different pathways in the sync network. These sync requests are sent to towards different masters in the sync network. If a fault occurs at a point in one of the paths, the gateway will still receive a sync acknowledgment returned along the other path. Furthermore, the use of redundant sync networks, propagating the sync requests across different paths, allows fault detection in the wiring to be detected.

Abstract: According to an aspect of the invention, there is provided a computer comprising a plurality of interconnected processing nodes arranged in a configuration with multiple stacked layers. Each layer comprises four processing nodes connected by respective links between the processing nodes. In end layers of the stack, the four processing nodes are interconnected in a ring formation by two links between the nodes, the two links adapted to operate simultaneously. Processing nodes in the multiple stacked layers provide four faces, each face comprising multiple layers, each layer comprising a pair of processing nodes. The processing nodes are programmed to operate a configuration to transmit data around embedded one-dimensional rings, each ring formed by processing nodes in two opposing faces.

Abstract: A data processing system comprising a plurality of processors, wherein each of the processors is configured to perform data transfer operations to transfer outgoing data to one or more others of the processors during a first of the exchange stages; receive incoming data from the one or more others of the processors during the first of the exchange stages; determine further outgoing data in dependence upon at least part of the incoming data; count an amount of at least part the incoming data received during the first of the exchange stages from the one or more others of the processors; and in response to determining that the amount of the at least part of the incoming data received has reached a predefined amount, perform data transfer operations to transfer the further outgoing data to the one or more others of the processors during a second of the exchange stages.

Abstract: A processor in a network has a plurality of processing units arranged on a chip. An on-chip interconnect enables data to be exchanged between the processing units. A plurality of external interfaces are configured to communicate data off chip in the form of packets, each packet having a destination address identifying a destination of the packet. The external interfaces are connected to respective additional connected processors. A routing bus routes packets between the processing units and the external interfaces. A routing register defines a routing domain for the processor, the routing domain comprising one or more of the additional processor, and at least a subset of further additional processors of the network, wherein the additional processors of the subset are directly or indirectly connected to the processor. The routing domain can be modified by changing the contents of the routing register as a sliding window domain.

Abstract: A multi-tile processing unit in which the tiles in the processing unit may be divided between two or more different external sync groups for performing barrier synchronisations. In this way, different sets of tiles of the same processing unit each sync with different sets of tiles external to that processing unit.

Abstract: The provision of redundancy in a sync network, which protects the sync network against faults, such as broken cables in the sync network. The gateway comprises a sync propagation module configured to provide redundant sync requests that are sent along different pathways in the sync network. These sync requests are sent to towards different masters in the sync network. If a fault occurs at a point in one of the paths, the gateway will still receive a sync acknowledgment returned along the other path. Furthermore, the use of redundant sync networks, propagating the sync requests across different paths, allows fault detection in the wiring to be detected.

Abstract: The provision of redundancy in a sync network, which protects the sync network against faults, such as broken cables in the sync network. The gateway comprises a sync propagation module configured to provide redundant sync requests that are sent along different pathways in the sync network. These sync requests are sent to towards different masters in the sync network. If a fault occurs at a point in one of the paths, the gateway will still receive a sync acknowledgment returned along the other path. Furthermore, the use of redundant sync networks, propagating the sync requests across different paths, allows fault detection in the wiring to be detected.

Abstract: A processor in a network has a plurality of processing units arranged on a chip. An on-chip interconnect enables data to be exchanged between the processing units. A plurality of external interfaces are configured to communicate data off chip in the form of packets, each packet having a destination address identifying a destination of the packet. The external interfaces are connected to respective additional connected processors. A routing bus routes packets between the processing units and the external interfaces. A routing register defines a routing domain for the processor, the routing domain comprising one or more of the additional processor, and at least a subset of further additional processors of the network, wherein the additional processors of the subset are directly or indirectly connected to the processor. The routing domain can be modified by changing the contents of the routing register as a sliding window domain.

Abstract: One aspect of the invention provides a computer comprising a plurality of interconnected processing nodes arranged in a ladder configuration comprising a plurality of facing pairs of processing nodes. The processing nodes of each pair are connected to each other by two links. A processing node in each pair is connected to a corresponding processing node in an adjacent pair by at least one link. The processing nodes are programmed to operate the ladder configuration to transmit data around two embedded one-dimensional rings formed by respective sets of processing nodes and links, each ring using all processing nodes in the ladder once only.

Abstract: A data processing system comprising a plurality of processors, wherein each of the processors is configured to perform data transfer operations to transfer outgoing data to one or more others of the processors during a first of the exchange stages; receive incoming data from the one or more others of the processors during the first of the exchange stages; determine further outgoing data in dependence upon at least part of the incoming data; count an amount of at least part the incoming data received during the first of the exchange stages from the one or more others of the processors; and in response to determining that the amount of the at least part of the incoming data received has reached a predefined amount, perform data transfer operations to transfer the further outgoing data to the one or more others of the processors during a second of the exchange stages.

Abstract: The provision of redundancy in a sync network, which protects the sync network against faults, such as broken cables in the sync network. The gateway comprises a sync propagation module configured to provide redundant sync requests that are sent along different pathways in the sync network. These sync requests are sent to towards different masters in the sync network. If a fault occurs at a point in one of the paths, the gateway will still receive a sync acknowledgment returned along the other path. Furthermore, the use of redundant sync networks, propagating the sync requests across different paths, allows fault detection in the wiring to be detected.

Abstract: Techniques for tracking completion of transfer requests. In one embodiment, a compute node connects to a network adapter (NA). In one embodiment, software running on the compute node contains instructions in which some remote data transfer requests belong to (or are associated with) completion groups. These completion groups may be constructed so that the system may more efficiently determine the completion status of remote transfer requests. In one embodiment, The NA includes a hardware counter for each completion group (CG). In one embodiment, the counter is configured to count when each transfer request in the completion group is received and when each request in the completion group is completed. For example, the counter may increment on receipt and decrement on completion such that a zero indicates completion of all requests in the completion group. In one embodiment, the NA includes a flush register to indicate whether the counter is valid.

Abstract: A system and method can support multiple domains in an InfiniBand (IB) fabric. The IB fabric can include one or more subnets, wherein each said subnet contains one or more switch nodes. Additionally, at least one said subnet can be divided into one or more sub-subnets, wherein each said sub-subnet is managed by a separate sub-subnet manager that is associated with a unique management key, and wherein said one or more sub-subnets are connected by one or more sub-subnet gateway switch nodes, wherein each sub-subnet gateway switch node belongs to one sub-subnet.

Abstract: A method for transmitting a message includes a communication adapter receiving, from a transmitting device, a request to send the message. The method further includes modifying a maximum transfer unit (MTU) to obtain a modified MTU, transmitting, from the communication adapter to a receiving system, a first sub-unit of the message using the modified MTU, iteratively increasing the MTU for transmitting intermediate sub-units of the message until an MTU limit is reached, and transmitting, to the receiving system, the intermediate sub-units of the message. The intermediate sub-units are transmitted after the first sub-unit and before a second sub-unit. The method further includes transmitting, from the communication adapter to the receiving system, the second sub-unit to the receiving system using a full path MTU.

Abstract: Techniques for tracking completion of transfer requests. In one embodiment, a compute node connects to a network adapter (NA). In one embodiment, software running on the compute node contains instructions in which some remote data transfer requests belong to (or are associated with) completion groups. These completion groups may be constructed so that the system may more efficiently determine the completion status of remote transfer requests. In one embodiment, The NA includes a hardware counter for each completion group (CG). In one embodiment, the counter is configured to count when each transfer request in the completion group is received and when each request in the completion group is completed. For example, the counter may increment on receipt and decrement on completion such that a zero indicates completion of all requests in the completion group. In one embodiment, the NA includes a flush register to indicate whether the counter is valid.

Abstract: A method for transmitting a message includes a communication adapter receiving, from a transmitting device, a request to send the message. The method further includes modifying a maximum transfer unit (MTU) to obtain a modified MTU, transmitting, from the communication adapter to a receiving system, a first sub-unit of the message using the modified MTU, iteratively increasing the MTU for transmitting intermediate sub-units of the message until an MTU limit is reached, and transmitting, to the receiving system, the intermediate sub-units of the message. The intermediate sub-units are transmitted after the first sub-unit and before a second sub-unit. The method further includes transmitting, from the communication adapter to the receiving system, the second sub-unit to the receiving system using a full path MTU.

Abstract: A method for transmitting a message includes a communication adapter receiving, from a transmitting device, a request to send the message. The method further includes modifying a maximum transfer unit (MTU) to obtain a modified MTU, transmitting, from the communication adapter to a receiving system, a first sub-unit of the message using the modified MTU, iteratively increasing the MTU for transmitting intermediate sub-units of the message until an MTU limit is reached, and transmitting, to the receiving system, the intermediate sub-units of the message. The intermediate sub-units are transmitted after the first sub-unit and before a second sub-unit. The method further includes transmitting, from the communication adapter to the receiving system, the second sub-unit to the receiving system using a full path MTU.

Abstract: A system, comprising a compute node and coupled network adapter (NA), that supports improved data transfer request buffering and a more efficient method of determining the completion status of data transfer requests. Transfer requests received by the NA are stored in a first buffer then transmitted on a network interface. When significant network delays are detected and the first buffer is full, the NA sets a flag to stop software issuing transfer requests. Compliant software checks this flag before sending requests and does not issue further requests. A second NA buffer stores additional received transfer requests that were perhaps in-transit. When conditions improve the flag is cleared and the first buffer used again. Completion status is efficiently determined by grouping network transfer requests. The NA counts received requests and completed network requests for each group. Software determines if a group of requests is complete by reading a count value.