Patents by Inventor Lars S. Carlson

Lars S. Carlson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100038738
    Abstract: An indirect connection to and across a photodiode array. The backside contact is used as one portion which connects to a capacitor. The capacitor forms a shunt across the bulk substrate, thus shunting across the series resistance of the substrate, and reducing the series resistance.
    Type: Application
    Filed: October 20, 2009
    Publication date: February 18, 2010
    Applicant: DIGIRAD CORPORATION
    Inventors: Joel Kindem, Lars S. Carlson
  • Patent number: 7605397
    Abstract: An indirect connection to and across a photodiode array. The backside contact is used as one portion which connects to a capacitor. The capacitor forms a shunt across the bulk substrate, thus shunting across the series resistance of the substrate, and reducing the series resistance.
    Type: Grant
    Filed: August 14, 2006
    Date of Patent: October 20, 2009
    Assignee: Digirad Corporation
    Inventors: Joel Kindem, Lars S. Carlson
  • Patent number: 7417216
    Abstract: Ultra-low leakage current backside-illuminated semiconductor photodiode arrays are fabricated using a method of formation of a transparent, conducting bias electrode layer that avoids high-temperature processing of the substrate after the wafer has been gettered. As a consequence, the component of the reverse-bias leakage current associated with strain, crystallographic defects or impurities introduced during elevated temperature processing subsequent to gettering can be kept extremely low. An optically transparent, conductive bias electrode layer, serving as both an optical window and an ohmic backside equipotential contact surface for the photodiodes, is fabricated by etching through the polysilicon gettering layer and a portion of the thickness of heavily-doped crystalline silicon layer formed within, and near the back of, the substrate during the gettering process.
    Type: Grant
    Filed: March 21, 2006
    Date of Patent: August 26, 2008
    Assignee: Digirad Corporation
    Inventors: Lars S. Carlson, Shulai Zhao, John Sheridan, Alan Mollet
  • Patent number: 7297927
    Abstract: Ultra-low leakage current backside-illuminated semiconductor photodiode arrays are fabricated using a method of formation of a transparent, conducting bias electrode layer that avoids high-temperature processing of the substrate after the wafer has been gettered. As a consequence, the component of the reverse-bias leakage current associated with strain, crystallographic defects or impurities introduced during elevated temperature processing subsequent to gettering can be kept extremely low. An optically transparent, conductive bias electrode layer, serving as both an optical window and an ohmic backside equipotential contact surface for the photodiodes, is fabricated by etching through the polysilicon gettering layer and a portion of the thickness of heavily-doped crystalline silicon layer formed within, and near the back of, the substrate during the gettering process.
    Type: Grant
    Filed: August 31, 2006
    Date of Patent: November 20, 2007
    Assignee: Digirad Corporation
    Inventors: Lars S. Carlson, Shulai Zhao, John Sheridan, Alan Mollet
  • Patent number: 7256386
    Abstract: Ultra-low leakage current backside-illuminated semiconductor photodiode arrays are fabricated using a method of formation of a transparent, conducting bias electrode layer that avoids high-temperature processing of the substrate after the wafer has been gettered. As a consequence, the component of the reverse-bias leakage current associated with strain, crystallographic defects or impurities introduced during elevated temperature processing subsequent to gettering can be kept extremely low. An optically transparent, conductive bias electrode layer, serving as both an optical window and an ohmic backside equipotential contact surface for the photodiodes, is fabricated by etching through the polysilicon gettering layer and a portion of the thickness of heavily-doped crystalline silicon layer formed within, and near the back of, the substrate during the gettering process.
    Type: Grant
    Filed: May 10, 2004
    Date of Patent: August 14, 2007
    Assignee: Digirad Corporation
    Inventors: Lars S. Carlson, Shulai Zhao, John Sheridan, Alan Mollet
  • Patent number: 7217953
    Abstract: A passive mechanism suppresses injection, into any active guard regions interposed between the edge of a photodiode array chip and the outer photodiode pixels or into the outer pixels themselves, of minority carrier current generated in the physically disrupted region at the edge of the semiconductor die created by cleaving, sawing or otherwise separating the chip from the remainder of the wafer on which the die was fabricated. A thin metallic layer covers all or part of the edge region, thereby creating a Schottky barrier. This barrier generates a depletion region in the adjacent semiconductor material. The depletion region inherently creates an energy band distribution which preferentially accelerates minority carriers generated or near the metal-semiconductor interface towards the metal, thereby suppressing collection of these carriers by any active regions of the guard structure or by the photodiode pixels.
    Type: Grant
    Filed: September 28, 2004
    Date of Patent: May 15, 2007
    Assignee: Digirad Corporation
    Inventor: Lars S. Carlson
  • Patent number: 7019783
    Abstract: An embedded power supply for providing a voltage on a detector module within an imaging system provides the required potential to the module from charge stored on an output capacitor. Charge on the capacitor is replenished by injecting, commonly referred to as pumping, current into the capacitor by pulses of current generated by switching mode circuitry. Charge pumping into the capacitor is efficient because energy is stored in low-loss passive components and transferred into the low-loss output capacitor through low-impedance paths. Switching noise of the power supply is eliminated by turning off the charge pumping circuit during periods when such noise would disrupt the operation of the module, for example when the module is reading out image data. The output capacitor is large enough to supply the required voltage to the module for a certain period when the capacitor is not being pumped.
    Type: Grant
    Filed: October 4, 2004
    Date of Patent: March 28, 2006
    Assignee: Digirad Corporation
    Inventors: Joel Kindem, Lars S. Carlson
  • Publication number: 20040206886
    Abstract: Ultra-low leakage current backside-illuminated semiconductor photodiode arrays are fabricated using a method of formation of a transparent, conducting bias electrode layer that avoids high-temperature processing of the substrate after the wafer has been gettered. As a consequence, the component of the reverse-bias leakage current associated with strain, crystallographic defects or impurities introduced during elevated temperature processing subsequent to gettering can be kept extremely low. An optically transparent, conductive bias electrode layer, serving as both an optical window and an ohmic backside equipotential contact surface for the photodiodes, is fabricated by etching through the polysilicon gettering layer and a portion of the thickness of heavily-doped crystalline silicon layer formed within, and near the back of, the substrate during the gettering process.
    Type: Application
    Filed: May 10, 2004
    Publication date: October 21, 2004
    Applicant: Digirad Corporation, a Delaware corporation
    Inventors: Lars S. Carlson, Shulai Zhao, John Sheridan, Alan Mollet
  • Patent number: 6798034
    Abstract: A passive mechanism suppresses injection, into any active guard regions interposed between the edge of a photodiode array chip and the outer photodiode pixels or into the outer pixels themselves, of minority carrier current generated in the physically disrupted region at the edge of the semiconductor die created by cleaving, sawing or otherwise separating the chip from the remainder of the wafer on which the die was fabricated. A thin metallic layer covers all or part of the edge region, thereby creating a Schottky barrier. This barrier generates a depletion region in the adjacent semiconductor material. The depletion region inherently creates an energy band distribution which preferentially accelerates minority carriers generated or near the metal-semiconductor interface towards the metal, thereby suppressing collection of these carriers by any active regions of the guard structure or by the photodiode pixels.
    Type: Grant
    Filed: August 7, 2002
    Date of Patent: September 28, 2004
    Assignee: Diglrad Corporation
    Inventor: Lars S. Carlson
  • Patent number: 6734416
    Abstract: Ultra-low leakage current backside-illuminated semiconductor photodiode arrays are fabricated using a method of formation of a transparent, conducting bias electrode layer that avoids high-temperature processing of the substrate after the wafer has been gettered. As a consequence, the component of the reverse-bias leakage current associated with strain, crystallographic defects or impurities introduced during elevated temperature processing subsequent to gettering can be kept extremely low. An optically transparent, conductive bias electrode layer, serving as both an optical window and an ohmic backside equipotential contact surface for the photodiodes, is fabricated by etching through the polysilicon gettering layer and a portion of the thickness of heavily-doped crystalline silicon layer formed within, and near the back of, the substrate during the gettering process.
    Type: Grant
    Filed: November 15, 2002
    Date of Patent: May 11, 2004
    Assignee: Digirad Corporation
    Inventors: Lars S. Carlson, Shulai Zhao, John Sheridan, Alan Mollet
  • Patent number: 6677182
    Abstract: A passive mechanism suppresses injection, into any active guard regions interposed between the edge of a photodiode array chip and the outer photodiode pixels or into the outer pixels themselves, of minority carrier current generated in the physically disrupted region at the edge of the semiconductor die created by cleaving, sawing or otherwise separating the chip from the remainder of the wafer on which the die was fabricated. A thin metallic layer covers all or part of the edge region, thereby creating a Schottky barrier. This barrier generates a depletion region in the adjacent semiconductor material. The depletion region inherently creates an energy band distribution which preferentially accelerates minority carriers generated or near the metal-semiconductor interface towards the metal, thereby suppressing collection of these carriers by any active regions of the guard structure or by the photodiode pixels.
    Type: Grant
    Filed: April 20, 2001
    Date of Patent: January 13, 2004
    Assignee: Digirad Corporation
    Inventor: Lars S. Carlson
  • Patent number: 6670258
    Abstract: Ultra-low leakage current backside-illuminated semiconductor photodiode arrays are fabricated using a method of formation of a transparent, conducting bias electrode layer that avoids high-temperature processing of the substrate after the wafer has been gettered. As a consequence, the component of the reverse-bias leakage current associated with strain, crystallographic defects or impurities introduced during elevated temperature processing subsequent to gettering can be kept extremely low. An optically transparent, conductive bias electrode layer, serving as both an optical window and an ohmic backside equipotential contact surface for the photodiodes, is fabricated by etching through the polysilicon gettering layer and a portion of the thickness of heavily-doped crystalline silicon layer formed within, and near the back of, the substrate during the gettering process.
    Type: Grant
    Filed: April 20, 2001
    Date of Patent: December 30, 2003
    Assignee: Digirad Corporation
    Inventors: Lars S. Carlson, Shulai Zhao, John Sheridan, Alan Mollet
  • Patent number: 6630735
    Abstract: A semiconductor interconnection device having a semiconductor die, a plurality of epoxy bonds, and an array of insulating islands is disclosed. The semiconductor die has a plurality of conductive contacts. The plurality of epoxy bonds has a metallic substance such as silver. The epoxy bonds are configured to provide interconnection between the semiconductor die and an external structure. The plurality of epoxy bonds is selectively applied to the plurality of conductive contacts on the semiconductor die and corresponding conductive contacts on the external structure. The array of insulating islands is coupled to the plurality of conductive contacts. The islands are configured to prevent migration of the metallic substance from the plurality of epoxy bonds to the semiconductor die through the plurality of conductive contacts.
    Type: Grant
    Filed: April 7, 2000
    Date of Patent: October 7, 2003
    Assignee: Digirad Corporation
    Inventors: Lars S. Carlson, Shulai Zhao
  • Publication number: 20030059630
    Abstract: Ultra-low leakage current backside-illuminated semiconductor photodiode arrays are fabricated using a method of formation of a transparent, conducting bias electrode layer that avoids high-temperature processing of the substrate after the wafer has been gettered. As a consequence, the component of the reverse-bias leakage current associated with strain, crystallographic defects or impurities introduced during elevated temperature processing subsequent to gettering can be kept extremely low. An optically transparent, conductive bias electrode layer, serving as both an optical window and an ohmic backside equipotential contact surface for the photodiodes, is fabricated by etching through the polysilicon gettering layer and a portion of the thickness of heavily-doped crystalline silicon layer formed within, and near the back of, the substrate during the gettering process.
    Type: Application
    Filed: November 16, 2002
    Publication date: March 27, 2003
    Applicant: Digirad Coproation, a Delaware corporation
    Inventors: Lars S. Carlson, Shulai Zhao, John Sheridan, Alan Mollet
  • Patent number: 6504178
    Abstract: A semiconductor imaging device is disclosed. The device includes a substrate having at least first and second surfaces opposing each other, and a circuit layer. The substrate is doped to exhibit a first conductivity type. The substrate includes a conducting layer, a region, and a plurality of doped regions. The conducting layer includes a first type dopants incorporated near the first surface. The region includes a heavily doped area within the substrate near the second surface. The plurality of doped regions includes a second type dopants formed on the second surface. The circuit layer is formed over the second surface to provide gate contacts to and readout circuits for the plurality of doped regions. The readout circuit provides readout of optical signals from pixels.
    Type: Grant
    Filed: April 5, 2001
    Date of Patent: January 7, 2003
    Assignee: Digirad Corporation
    Inventors: Lars S. Carlson, Shulai Zhao, Richard Wilson
  • Publication number: 20020185654
    Abstract: A passive mechanism suppresses injection, into any active guard regions interposed between the edge of a photodiode array chip and the outer photodiode pixels or into the outer pixels themselves, of minority carrier current generated in the physically disrupted region at the edge of the semiconductor die created by cleaving, sawing or otherwise separating the chip from the remainder of the wafer on which the die was fabricated. A thin metallic layer covers all or part of the edge region, thereby creating a Schottky barrier. This barrier generates a depletion region in the adjacent semiconductor material. The depletion region inherently creates an energy band distribution which preferentially accelerates minority carriers generated or near the metal-semiconductor interface towards the metal, thereby suppressing collection of these carriers by any active regions of the guard structure or by the photodiode pixels.
    Type: Application
    Filed: August 7, 2002
    Publication date: December 12, 2002
    Applicant: Digirad Corporation, a Delaware corporation
    Inventor: Lars S. Carlson
  • Publication number: 20020011639
    Abstract: A semiconductor imaging device is disclosed. The device includes a substrate having at least first and second surfaces opposing each other, and a circuit layer. The substrate is doped to exhibit a first conductivity type. The substrate includes a conducting layer, a region, and a plurality of doped regions. The conducting layer includes a first type dopants incorporated near the first surface. The region includes a heavily doped area within the substrate near the second surface. The plurality of doped regions includes a second type dopants formed on the second surface. The circuit layer is formed over the second surface to provide gate contacts to and readout circuits for the plurality of doped regions. The readout circuit provides readout of optical signals from pixels.
    Type: Application
    Filed: April 5, 2001
    Publication date: January 31, 2002
    Inventors: Lars S. Carlson, Shulai Zhao, Richard Wilson
  • Publication number: 20020000562
    Abstract: Ultra-low leakage current backside-illuminated semiconductor photodiode arrays are fabricated using a method of formation of a transparent, conducting bias electrode layer that avoids high-temperature processing of the substrate after the wafer has been gettered. As a consequence, the component of the reverse-bias leakage current associated with strain, crystallographic defects or impurities introduced during elevated temperature processing subsequent to gettering can be kept extremely low. An optically transparent, conductive bias electrode layer, serving as both an optical window and an ohmic backside equipotential contact surface for the photodiodes, is fabricated by etching through the polysilicon gettering layer and a portion of the thickness of heavily-doped crystalline silicon layer formed within, and near the back of, the substrate during the gettering process.
    Type: Application
    Filed: April 20, 2001
    Publication date: January 3, 2002
    Inventors: Lars S. Carlson, Shulai Zhao, John Sheridan, Alan Mollet
  • Publication number: 20010034105
    Abstract: A passive mechanism suppresses injection, into any active guard regions interposed between the edge of a photodiode array chip and the outer photodiode pixels or into the outer pixels themselves, of minority carrier current generated in the physically disrupted region at the edge of the semiconductor die created by cleaving, sawing or otherwise separating the chip from the remainder of the wafer on which the die was fabricated. A thin metallic layer covers all or part of the edge region, thereby creating a Schottky barrier. This barrier generates a depletion region in the adjacent semiconductor material. The depletion region inherently creates an energy band distribution which preferentially accelerates minority carriers generated or near the metal-semiconductor interface towards the metal, thereby suppressing collection of these carriers by any active regions of the guard structure or by the photodiode pixels.
    Type: Application
    Filed: April 20, 2001
    Publication date: October 25, 2001
    Inventor: Lars S. Carlson
  • Publication number: 20010029061
    Abstract: A semiconductor interconnection device having a semiconductor die, a plurality of epoxy bonds, and an array of insulating islands is disclosed. The semiconductor die has a plurality of conductive contacts. The plurality of epoxy bonds has a metallic substance such as silver. The epoxy bonds are configured to provide interconnection between the semiconductor die and an external structure. The plurality of epoxy bonds is selectively applied to the plurality of conductive contacts on the semiconductor die and corresponding conductive contacts on the external structure. The array of insulating islands is coupled to the plurality of conductive contacts. The islands are configured to prevent migration of the metallic substance from the plurality of epoxy bonds to the semiconductor die through the plurality of conductive contacts.
    Type: Application
    Filed: March 26, 2001
    Publication date: October 11, 2001
    Inventors: Lars S. Carlson, Shulai Zhao