Patents by Inventor Lars Wolfgang Liebmann
Lars Wolfgang Liebmann has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10446653Abstract: A semiconductor structure includes a semiconductor substrate, a semiconductor fin on the semiconductor substrate, a transistor integrated with the semiconductor fin at a top portion thereof, the transistor including an active region including a source, a drain and a channel region therebetween. The semiconductor structure further includes a gate structure over the channel region, the gate structure including a gate electrode, an air-gap spacer pair on opposite sidewalls of the gate electrode, and a gate contact for the gate electrode. A method of fabricating such a semiconductor device is also provided.Type: GrantFiled: November 15, 2016Date of Patent: October 15, 2019Assignee: GLOBALFOUNDRIES INC.Inventors: Ruilong Xie, Min Gyu Sung, Chanro Park, Lars Wolfgang Liebmann, Hoon Kim
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Publication number: 20180138279Abstract: A semiconductor structure includes a semiconductor substrate, a semiconductor fin on the semiconductor substrate, a transistor integrated with the semiconductor fin at a top portion thereof, the transistor including an active region including a source, a drain and a channel region therebetween. The semiconductor structure further includes a gate structure over the channel region, the gate structure including a gate electrode, an air-gap spacer pair on opposite sidewalls of the gate electrode, and a gate contact for the gate electrode. A method of fabricating such a semiconductor device is also provided.Type: ApplicationFiled: November 15, 2016Publication date: May 17, 2018Applicant: GLOBALFOUNDRIES Inc.Inventors: Ruilong XIE, Min Gyu SUNG, Chanro PARK, Lars Wolfgang LIEBMANN, Hoon KIM
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Patent number: 9812351Abstract: A method includes patterning a 1st mandrel cell into a 1st mandrel layer disposed above a dielectric layer of a semiconductor structure. The 1st mandrel cell has 1st mandrels, 1st mandrel spaces and a mandrel cell pitch. A 2nd mandrel cell is patterned into a 2nd mandrel layer disposed above the 1st mandrel layer. The 2nd mandrel cell has 2nd mandrels, 2nd mandrel spaces, and the mandrel cell pitch. The 1st and 2nd mandrel cells are utilized to form metal line cells into the dielectric layer. The metal line cells have metal lines, spaces between the metal lines and a line cell pitch. The line cell pitch is equal to the mandrel cell pitch when the metal lines of the metal line cells are an even number. The line cell pitch is equal to half the mandrel cell pitch when the metal lines of the metal line cells are an odd number.Type: GrantFiled: December 15, 2016Date of Patent: November 7, 2017Assignee: GLOBALFOUNDRIES Inc.Inventors: Nicholas Vincent Licausi, Guillaume Bouche, Lars Wolfgang Liebmann
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Publication number: 20150145041Abstract: A substrate local interconnect structure and method is disclosed. A buried conductor is formed in the insulator region or on the semiconductor substrate. The buried conductor may be formed by metal deposition, doped silicon regions, or silciding a region of the substrate. Metal sidewall portions connect transistor contacts to the buried conductor to form interconnections without the use of middle-of-line (MOL) metallization and via layers.Type: ApplicationFiled: November 22, 2013Publication date: May 28, 2015Applicant: International Business Machines CorporationInventors: Ramachandra Divakaruni, Lars Wolfgang Liebmann, Shom Ponoth, Balasubramanian Pranatharthiharan, Scott R. Stiffler
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Publication number: 20130159955Abstract: A method, system, and computer program product for improving pin access in a design of an integrated circuit (IC) for multi-patterning lithography (MPL) are provided in the illustrative embodiments. A cell is placed in the IC design, the cell including a pin shape configured to connect a pin of the cell to a semi-conductor component in the IC design, the cell including a coloring conflict due to the pin shape and an other shape in the cell each being colored using a first color for fabricating onto a wafer using MPL. A net is routed to the pin shape without resolving the coloring conflict, wherein the routing routes the net using a first segment of the pin shape. The pin shape is modified after routing to resolve the coloring conflict to result in a modified cell.Type: ApplicationFiled: December 16, 2011Publication date: June 20, 2013Applicant: International Business Machines CorporationInventors: Rani Abou Ghaida, Kanak Behari Agarwal, Lars Wolfgang Liebmann, Sani Richard Nassif
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Patent number: 6185727Abstract: A checking routine verifies a phase shifted mask (PSM) design based on fundamental principles of PSM and utilizing only basic shape manipulation functions and Boolean operations found in most computer aided design (CAD) systems. The design verification system checks complete chip designs for the two possible design errors that can cause defective masks by eliminating the phase transition; namely, placing a 180° phase region on both sides of a critical feature or completely omitting the phase region adjacent to certain critical features.Type: GrantFiled: December 12, 1995Date of Patent: February 6, 2001Assignee: International Business Machines CorporationInventor: Lars Wolfgang Liebmann
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Patent number: 6055367Abstract: A method is provided that automatically generates compensated semiconductor devices based on existing VLSI CAD database circuit designs. The preferred method forms a plurality of edge projection shapes which are intersected with active area shapes to form gate edge shapes. The gate edge shapes and residual of the edge shapes are the sorted according to their relative position. These shapes are then selectively biased according to their relative position, and then are used to compensate the existing gate conductor shapes. Thus, this method provides a way to generate gate structures with compensated gate lengths for n-channel and p-channel devices based on existing gate, diffusion and implant designs. This system has the advantage of generating designs with detailed attention to the placement and minimization of jogs that negatively impact the lithography performance.Type: GrantFiled: February 16, 1999Date of Patent: April 25, 2000Assignee: International Business Machines CorporationInventors: Lars Wolfgang Liebmann, Robert T. Sayah
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Patent number: 5877964Abstract: A method is provided that automatically generates compensated semiconductor devices based on existing VLSI CAD database circuit designs. The preferred method forms a plurality of edge projection shapes which are intersected with active area shapes to form gate edge shapes. The gate edge shapes and residual of the edge shapes are the sorted according to their relative position. These shapes are then selectively biased according to their relative position, and then are used to compensate the existing gate conductor shapes. Thus, this method provides a way to generate gate structures with compensated gate lengths for n-channel and p-channel devices based on existing gate, diffusion and implant designs. This system has the advantage of generating designs with detailed attention to the placement and minimization of jogs that negatively impact the lithography performance.Type: GrantFiled: January 10, 1997Date of Patent: March 2, 1999Assignee: International Business Machines CorporationInventors: Lars Wolfgang Liebmann, Robert T. Sayah
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Patent number: 5740068Abstract: A method for performing optical proximity correction is disclosed that not only limits the optical proximity correction to electrically relevant structures, but also improves the accuracy of the corrections by processing individual feature edges, and minimizes the mask manufacturing impacts by avoiding the introduction of jogs into the design. Critical edge regions of the relevant electrical structures are analyzed, sorted and manipulated to receive optical proximity corrections.Type: GrantFiled: May 30, 1996Date of Patent: April 14, 1998Assignee: International Business Machines CorporationInventors: Lars Wolfgang Liebmann, Robert Thomas Sayah, John Edward Barth, Jr.
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Patent number: 5657235Abstract: Energy levels (dose) are manipulated to modify the resultant photomask representation in a controlled manner such that the final image in the semiconductor device fabrication is close to an ideal image. Feature sizes and shapes are modified by assigning relative mask writer doses rather than physically manipulating feature sizes in layout designs. This approach, based on coding of relative dose information onto the design data, allows continuous scale line width variation for all features without impact to data volume. Two embodiments are described. In the first embodiment, distortion knowledge in the form of a lookup table or convolution function is applied to CAD data which is fractured into numerous designs having specific dose assignments. In the alternative embodiment, distortion knowledge in the form of a lookup table or convolution function is applied to CAD data which generates an attribute file containing hierarchical dose information that is mapped onto the mask data.Type: GrantFiled: May 3, 1995Date of Patent: August 12, 1997Assignee: International Business Machines CorporationInventors: Lars Wolfgang Liebmann, Ronald Michael Martino, J. Tracy Weed