Patents by Inventor Larson Lindholm
Larson Lindholm has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9219001Abstract: Fin-FET (fin field-effect transistor) devices and methods of fabrication are disclosed. The fin-FET devices include dual fin structures that may form a channel region between a source region and a drain region. In some embodiments, the dual fin structures are formed by forming shallow trench isolation structures, using a pair of shallow trench isolation (STI) structures as a mask to define a recess in a portion of a substrate between the pair of STI structures, and recessing the pair of STI structures so that the resulting dual fin structures protrude from an active surface of the substrate. The dual fin structures may be used to form single-gate, double-gate, or triple-gate fin-FET devices. Electronic systems including such fin-FET devices are also disclosed.Type: GrantFiled: July 26, 2013Date of Patent: December 22, 2015Assignee: Micron Technology, Inc.Inventors: Aaron R. Wilson, Larson Lindholm, David Hwang
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Patent number: 9041086Abstract: A method of forming a vertical field effect transistor includes etching an opening into semiconductor material. Sidewalls and radially outermost portions of the opening base are lined with masking material. A semiconductive material pillar is epitaxially grown to within the opening adjacent the masking material from the semiconductor material at the opening base. At least some of the masking material is removed from the opening. A gate dielectric is formed radially about the pillar. Conductive gate material is formed radially about the gate dielectric. An upper portion of the pillar is formed to comprise one source/drain region of the vertical transistor. Semiconductive material of the pillar received below the upper portion is formed to comprise a channel region of the vertical transistor. Semiconductor material adjacent the opening is formed to comprise another source/drain region of the vertical transistor. Other aspects and implementations are contemplated.Type: GrantFiled: June 4, 2012Date of Patent: May 26, 2015Assignee: Micron Technology, Inc.Inventors: Larson Lindholm, David Hwang
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Publication number: 20130309839Abstract: Fin-FET (fin field-effect transistor) devices and methods of fabrication are disclosed. The fin-FET devices include dual fin structures that may form a channel region between a source region and a drain region. In some embodiments, the dual fin structures are formed by forming shallow trench isolation structures, using a pair of shallow trench isolation (STI) structures as a mask to define a recess in a portion of a substrate between the pair of STI structures, and recessing the pair of STI structures so that the resulting dual fin structures protrude from an active surface of the substrate. The dual fin structures may be used to form single-gate, double-gate, or triple-gate fin-FET devices. Electronic systems including such fin-FET devices are also disclosed.Type: ApplicationFiled: July 26, 2013Publication date: November 21, 2013Applicant: Micron Technology, Inc.Inventors: Aaron R. Wilson, Larson Lindholm, David Hwang
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Patent number: 8497530Abstract: Fin-FET (fin field-effect transistor) devices and methods of fabrication are disclosed. The fin-FET devices include dual fin structures that may form a channel region between a source region and a drain region. In some embodiments, the dual fin structures are formed by forming shallow trench isolation structures, using a pair of shallow trench isolation (STI) structures as a mask to define a recess in a portion of a substrate between the pair of STI structures, and recessing the pair of STI structures so that the resulting dual fin structures protrude from an active surface of the substrate. The dual fin structures may be used to form single-gate, double-gate, or triple-gate fin-FET devices. Electronic systems including such fin-FET devices are also disclosed.Type: GrantFiled: March 19, 2012Date of Patent: July 30, 2013Assignee: Micron Technology, Inc.Inventors: Aaron R. Wilson, Larson Lindholm, David Hwang
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Publication number: 20120241831Abstract: A method of forming a vertical field effect transistor includes etching an opening into semiconductor material. Sidewalls and radially outermost portions of the opening base are lined with masking material. A semiconductive material pillar is epitaxially grown to within the opening adjacent the masking material from the semiconductor material at the opening base. At least some of the masking material is removed from the opening. A gate dielectric is formed radially about the pillar. Conductive gate material is formed radially about the gate dielectric. An upper portion of the pillar is formed to comprise one source/drain region of the vertical transistor. Semiconductive material of the pillar received below the upper portion is formed to comprise a channel region of the vertical transistor. Semiconductor material adjacent the opening is formed to comprise another source/drain region of the vertical transistor. Other aspects and implementations are contemplated.Type: ApplicationFiled: June 4, 2012Publication date: September 27, 2012Applicant: MICRON TECHNOLOGY, INC.Inventors: Larson Lindholm, David Hwang
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Publication number: 20120175748Abstract: Fin-FET (fin field effect transistor) devices and methods of fabrication are disclosed. The Fin-FET devices include dual fin structures that may form a channel region between a source region and a drain region. In some embodiments, the dual fin structures are formed by forming shallow trench isolation structures, using a pair of shallow trench isolation (STI) structures as a mask to define a recess in a portion of the substrate between the pair of STI structures, and recessing the pair of STI structures so that the resulting dual fin structure protrudes from an active surface of the substrate. The dual fin structure may be used to form single-gate, double-gate, or triple-gate fin-FET devices. Electronic systems including such fin-FET devices are also disclosed.Type: ApplicationFiled: March 19, 2012Publication date: July 12, 2012Applicant: MICRON TECHNOLOGY, INC.Inventors: Aaron R. Wilson, Larson Lindholm, David Hwang
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Patent number: 8178911Abstract: A semiconductor device fabricated in the semiconductor substrate includes a FinFET transistor having opposed source and drain pillars, and a fin interposed between the source and drain pillars. A cavity is formed in the semiconductor substrate extending at least partially between the fin and the semiconductor substrate. The cavity may be formed within a shallow trench isolation structure, and it may also extend at least partially between the semiconductor substrate and one or both of the pillars. The cavities increase the impedance between the semiconductor substrate and the fin and/or pillars to decrease the sub-threshold leakage of the FinFET transistor.Type: GrantFiled: September 8, 2011Date of Patent: May 15, 2012Assignee: Micron Technology, Inc.Inventors: David K. Hwang, Larson Lindholm
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Patent number: 8138526Abstract: Fin-FET (fin field effect transistor) devices and methods of fabrication are disclosed. The Fin-FET devices include dual fin structures that may form a channel region between a source region and a drain region. In some embodiments, the dual fin structures are formed by thinning shallow trench isolation structures, using a pair of shallow trench isolation (STI) structures as a mask to define a recess in a portion of the substrate between the pair of STI structures, and recessing the pair of STI structures so that the resulting dual fin structure protrudes from an active surface of the substrate. The dual fin structure may be used to form single-gate, double-gate or triple-gate fin-FET devices. Electronic systems including such fin-FET devices are also disclosed.Type: GrantFiled: November 11, 2010Date of Patent: March 20, 2012Assignee: Micron Technology, Inc.Inventors: Aaron R. Wilson, Larson Lindholm, David Hwang
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Publication number: 20120003810Abstract: A semiconductor device fabricated in the semiconductor substrate includes a FinFET transistor having opposed source and drain pillars, and a fin interposed between the source and drain pillars. A cavity is formed in the semiconductor substrate extending at least partially between the fin and the semiconductor substrate. The cavity may be formed within a shallow trench isolation structure, and it may also extend at least partially between the semiconductor substrate and one or both of the pillars. The cavities increase the impedance between the semiconductor substrate and the fin and/or pillars to decrease the sub-threshold leakage of the FinFET transistor.Type: ApplicationFiled: September 8, 2011Publication date: January 5, 2012Applicant: Micron Technology, Inc.Inventors: David K. Hwang, Larson Lindholm
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Patent number: 8022473Abstract: A semiconductor device fabricated in the semiconductor substrate includes a FinFET transistor having opposed source and drain pillars, and a fin interposed between the source and drain pillars. A cavity is formed in the semiconductor substrate extending at least partially between the fin and the semiconductor substrate. The cavity may be formed within a shallow trench isolation structure, and it may also extend at least partially between the semiconductor substrate and one or both of the pillars. The cavities increase the impedance between the semiconductor substrate and the fin and/or pillars to decrease the sub-threshold leakage of the FinFET transistor.Type: GrantFiled: February 16, 2011Date of Patent: September 20, 2011Assignee: Micron Technology, Inc.Inventors: David K. Hwang, Larson Lindholm
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Publication number: 20110140187Abstract: A method of forming a vertical field effect transistor includes etching an opening into semiconductor material. Sidewalls and radially outermost portions of the opening base are lined with masking material. A semiconductive material pillar is epitaxially grown to within the opening adjacent the masking material from the semiconductor material at the opening base. At least some of the masking material is removed from the opening. A gate dielectric is formed radially about the pillar. Conductive gate material is formed radially about the gate dielectric. An upper portion of the pillar is formed to comprise one source/drain region of the vertical transistor. Semiconductive material of the pillar received below the upper portion is formed to comprise a channel region of the vertical transistor. Semiconductor material adjacent the opening is formed to comprise another source/drain region of the vertical transistor. Other aspects and implementations are contemplated.Type: ApplicationFiled: February 28, 2011Publication date: June 16, 2011Applicant: Micron Technology, Inc.Inventors: Larson Lindholm, David Hwang
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Publication number: 20110133263Abstract: A semiconductor device fabricated in the semiconductor substrate includes a FinFET transistor having opposed source and drain pillars, and a fin interposed between the source and drain pillars. A cavity is formed in the semiconductor substrate extending at least partially between the fin and the semiconductor substrate. The cavity may be formed within a shallow trench isolation structure, and it may also extend at least partially between the semiconductor substrate and one or both of the pillars. The cavities increase the impedance between the semiconductor substrate and the fin and/or pillars to decrease the sub-threshold leakage of the FinFET transistor.Type: ApplicationFiled: February 16, 2011Publication date: June 9, 2011Applicant: Micron Technology, Inc.Inventors: DAVID K. HWANG, Larson Lindholm
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Patent number: 7948030Abstract: Some embodiments include methods of recessing multiple materials to a common depth utilizing etchant comprising C4F6 and C4F3. The recessed materials may be within isolation regions, and the recessing may be utilized to form trenches for receiving gatelines. Some embodiments include structures having an island of semiconductor material laterally surrounded by electrically insulative material. Two gatelines extend across the insulative material and across the island of semiconductor material. One of the gatelines is recessed deeper into the electrically insulative material than the other.Type: GrantFiled: September 3, 2010Date of Patent: May 24, 2011Assignee: Micron Technology, Inc.Inventors: Larson Lindholm, Aaron R. Wilson, David K. Hwang
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Patent number: 7910971Abstract: A method of forming a vertical field effect transistor includes etching an opening into semiconductor material. Sidewalls and radially outermost portions of the opening base are lined with masking material. A semiconductive material pillar is epitaxially grown to within the opening adjacent the masking material from the semiconductor material at the opening base. At least some of the masking material is removed from the opening. A gate dielectric is formed radially about the pillar. Conductive gate material is formed radially about the gate dielectric. An upper portion of the pillar is formed to comprise one source/drain region of the vertical transistor. Semiconductive material of the pillar received below the upper portion is formed to comprise a channel region of the vertical transistor. Semiconductor material adjacent the opening is formed to comprise another source/drain region of the vertical transistor. Other aspects and implementations are contemplated.Type: GrantFiled: August 7, 2008Date of Patent: March 22, 2011Assignee: Micron Technology, Inc.Inventors: Larson Lindholm, David Hwang
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Publication number: 20110057269Abstract: Fin-FET (fin field effect transistor) devices and methods of fabrication are disclosed. The Fin-FET devices include dual fin structures that may form a channel region between a source region and a drain region. In some embodiments, the dual fin structures are formed by thinning shallow trench isolation structures, using a pair of shallow trench isolation (STI) structures as a mask to define a recess in a portion of the substrate between the pair of STI structures, and recessing the STI structures so that the resulting dual fin structure protrudes from an active surface of the substrate. The dual fin structure may be used to form single-gate, double-gate or triple-gate fin-FET devices. Electronic systems including such fin-FET devices are also disclosed.Type: ApplicationFiled: November 11, 2010Publication date: March 10, 2011Applicant: MICRON TECHNOLOGY, INC.Inventors: Aaron R. Wilson, Larson Lindholm, David Hwang
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Patent number: 7897465Abstract: A semiconductor device fabricated in the semiconductor substrate includes a FinFET transistor having opposed source and drain pillars, and a fin interposed between the source and drain pillars. A cavity is formed in the semiconductor substrate extending at least partially between the fin and the semiconductor substrate. The cavity may be formed within a shallow trench isolation structure, and it may also extend at least partially between the semiconductor substrate and one or both of the pillars. The cavities increase the impedance between the semiconductor substrate and the fin and/or pillars to decrease the sub-threshold leakage of the FinFET transistor.Type: GrantFiled: March 15, 2010Date of Patent: March 1, 2011Assignee: Micron Technology, Inc.Inventors: David K. Hwang, Larson Lindholm
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Patent number: 7879659Abstract: Fin-FET (fin field effect transistor) devices and methods of fabrication are disclosed. The Fin-FET devices include dual fin structures that may form a channel region between a source region and a drain region. In some embodiments, the dual fin structures are formed by forming shallow trench isolation structures, using a pair of shallow trench isolation (STI) structures as a mask to define a recess in a portion of the substrate between the pair of STI structures, and recessing the STI structures so that the resulting dual fin structure protrudes from an active surface of the substrate. The dual fin structure may be used to form single-gate, double-gate or triple-gate fin-FET devices. Electronic systems including such fin-FET devices are also disclosed.Type: GrantFiled: July 17, 2007Date of Patent: February 1, 2011Assignee: Micron Technology, Inc.Inventors: Aaron R. Wilson, Larson Lindholm, David Hwang
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Publication number: 20100327369Abstract: Some embodiments include methods of recessing multiple materials to a common depth utilizing etchant comprising C4F6 and C4F3. The recessed materials may be within isolation regions, and the recessing may be utilized to form trenches for receiving gatelines. Some embodiments include structures having an island of semiconductor material laterally surrounded by electrically insulative material. Two gatelines extend across the insulative material and across the island of semiconductor material. One of the gatelines is recessed deeper into the electrically insulative material than the other.Type: ApplicationFiled: September 3, 2010Publication date: December 30, 2010Applicant: MICRON TECHNOLOGY, INC.Inventors: Larson Lindholm, Aaron R. Wilson, David K. Hwang
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Patent number: 7808041Abstract: Some embodiments include methods of recessing multiple materials to a common depth utilizing etchant comprising C4F6 and C4F8. The recessed materials may be within isolation regions, and the recessing may be utilized to form trenches for receiving gatelines. Some embodiments include structures having an island of semiconductor material laterally surrounded by electrically insulative material. Two gatelines extend across the insulative material and across the island of semiconductor material. One of the gatelines is recessed deeper into the electrically insulative material than the other.Type: GrantFiled: December 1, 2009Date of Patent: October 5, 2010Assignee: Micron Technology, Inc.Inventors: Larson Lindholm, Aaron R. Wilson, David K. Hwang
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Publication number: 20100171170Abstract: A semiconductor device fabricated in the semiconductor substrate includes a FinFET transistor having opposed source and drain pillars, and a fin interposed between the source and drain pillars. A cavity is formed in the semiconductor substrate extending at least partially between the fin and the semiconductor substrate. The cavity may be formed within a shallow trench isolation structure, and it may also extend at least partially between the semiconductor substrate and one or both of the pillars. The cavities increase the impedance between the semiconductor substrate and the fin and/or pillars to decrease the sub-threshold leakage of the FinFET transistor.Type: ApplicationFiled: March 15, 2010Publication date: July 8, 2010Applicant: Micron Technology, Inc.Inventors: David K. Hwang, Larson Lindholm