Abstract: The invention relates to a method for storing data in a memory of a cooking appliance and/or for reading data from the memory of the cooking appliance, wherein the cooking appliance comprises at least one interface to a server. In a first step, data of the cooking appliance is stored in the memory, and in a second step, following authentication by the server in relation to the cooking appliance, data is read from the memory by the server via encoded data transmission. The invention further relates to a cooking appliance, comprising at least one memory, a user interface, and at least one interface to at least one server in order to carry out such a method for the purpose of transmitting data between the memory and at least the server.

Abstract: A system for synchronous monitoring of a cooking process of a plurality of cooking devices via the internal web browser of one of the cooking devices comprises a plurality of cooking devices that can be interconnected via interfaces. Each cooking device is connected to at least one internal web server that is connected to a network and that provides services for the monitoring, control or analysis of at least one of the cooking devices. At least one internal web browser is provided that is connected to the network and that can use at least the services of one of the internal web servers.

Abstract: A method of calibrating a timebase in a digitizing instrument estimates the frequency of the clock signal from the clock generator that clocks a coarse delay counter in a strobe generator. The dynamic range of the interpolator in the strobe generator is defined in digital-to-analog converter code values as a function of the clock signal period. A linear horizontal look-up table of equally spaced digital-to-analog converter code values is generated over the defined dynamic range of the interpolator. Residual nonlinearities of the interpolator over the defined dynamic range of the interpolator are characterized and scaled to digital-to-analog converter code values. The digital-to-analog converter code values of the characterized residual anomalies are combined with the digital-to-analog converter code values of the linear horizontal look-up table to generate a horizontal look-up table having DAC code value compensating for the nonlinearities of the interpolator.

Abstract: A phase stable clock circuit includes a phase gate having track-and-hold (T/H) circuits with each T/H circuit receiving a phase shifted continuous sinusoidal signal of predetermined phase and a control input signal to capture and hold phase samples of the sinusoidal signals. In alternative embodiments, a phase correction circuit provides phase correction values that are added to the held phase values to generate corrected phase values and time-error phase lookup table is used to generate time position correction values. The corrected phase values are applied to the phase gate remove deterministic phase errors to generate an output signal with a predetermined startup phase relative to the control input signal transition. The phase error-to-time lookup table adjusts the time placement of waveform record samples after the acquisition of the samples.

Abstract: A phase stable clock circuit includes a phase gate having track-and-hold (T/H) circuits with each T/H circuit receiving a phase shifted continuous sinusoidal signal of predetermined phase and a control input signal to hold, at a selected time during the signal epoch of the respective sinusoidal signals, phase values of the sinusoidal signals. The respective phase values are coupled to an infinite track-and-hold circuit to generate replicas of the phase values. The phase values and the replica phase values are coupled to respective multiplexers that selectively couple the phase values to multipliers during a first time period and replica phase values during a second time period. The output of each multiplexer is coupled to a multiplier that receives one of the phase shifted continuous sinusoidal signals. The output of the multipliers are summed in a summing circuit to generate an output signal with a predetermined stable startup phase relative to the transition.