Abstract: An apparatus includes: a plurality of bit producing circuits; a controller setting a sample frequency at which bits from the bit producing circuits are sampled; and a plurality of test circuits determining if bits sampled from each of the bit producing circuits are random, wherein the controller adjusts the sample frequency if the test circuits determine that the sampled bits are not random. A method performed by the apparatus is also included.

Abstract: An encryption scheme for mass storage devices employing a tweakable encryption scheme to add variability to the encrypted data to resist attacks by traffic analysis. Explicit tweak and implicit tweak may be used to add variability to plaintext prior to encryption and eventual storage. The tweak information is either stored on the storage device along with the encrypted data as in the case of an explicit tweak, or it is derived from another source when needed as in the case of an implicit tweak. The ciphertext is decrypted using either the stored explicit tweak value or derive the implicit tweak value to “de-tweak” the decrypted data prior to usage. The data may be deleted by destroying the cipher key(s) to render the ciphertext useless. The tweak information alone is useless for decryption, as the ciphertext needs to be decrypted with the cipher key(s).

Abstract: An apparatus comprises a data storage medium including first and second partitions, wherein individual physical blocks in the first partition are paired with individual physical blocks in the second partition, a status flag for each of the pairs of physical blocks, and a controller for performing read and write operations on the physical blocks in accordance with the status flags. A method performed by the apparatus is also provided.

Abstract: An apparatus includes a first counter for counting successive bits representative of a logic 1, and a second counter for counting successive bits representative of a logic 0, wherein a first predetermined count on the first counter or a second predetermined count on the second counter indicates a randomness failure. A method for testing randomness performed by the apparatus is also included.

Abstract: An apparatus includes an oscillator, a counter for counting pulses, and a latch for latching a count from the counter in response to changes in a logic level of an output of the oscillator. The apparatus can further include an edge detector for producing a latching signal in response to changes in the logic level of the output of the oscillator.

Abstract: A method including: reading a portion of stored data from a storage medium, decrypting the portion of stored data, then if changes are requested, making the changes to the portion of stored data to produce changed data, encrypting the changed data, and writing the encrypted changed data to the storage medium. An apparatus that performs the method is also included.

Abstract: An apparatus comprises a data storage medium including first and second partitions, wherein individual physical blocks in the first partition are paired with individual physical blocks in the second partition, a status flag for each of the pairs of physical blocks, and a controller for performing read and write operations on the physical blocks in accordance with the status flags. A method performed by the apparatus is also provided.

Abstract: A storage device has a storage medium, a set of credentials stored on the storage medium, and a controller. The controller within the storage device is coupled to the storage medium, and adapted to identify security status of the storage device. The controller is adapted to alter one or more credentials of the set of credentials responsive to the security status.

Abstract: A method includes: computing a first message authentication code for each of a plurality of sets of data blocks on a data storage medium, and authenticating the sets of data blocks by computing a second message authentication code for each of the sets of data blocks to be authenticated and comparing the first and second message authentication codes. An apparatus that performs the method is also provided.

Abstract: An apparatus comprises at least one port for coupling signals to the apparatus, a mode selector for setting the apparatus to a normal mode or a debug mode, and a port control for controlling access to secure information in the apparatus through the port in accordance with the selected mode. A method for controlling access to the port is also provided.

Abstract: A method of encrypting information in a data storage device that includes a storage medium having a plurality of physical memory locations referenced through logical block addresses is provided. The method includes receiving, in the data storage device, data from a host computer. At least a portion of the received data is encrypted, within the data storage device, if the at least a portion of the received data is destined for storage in at least a subset of the plurality of physical memory locations, which correspond to a predetermined range of logical block addresses. The encryption of the at least a portion of the received data is substantially transparent to the host computer and independent of a file to which the at least a portion of the data belongs. In addition, a data storage device readable by a computer system for implementing the above encryption method is provided.

Abstract: A random number generator includes a plurality of groups of independent flip flops, each of the groups having different configurations. Each of the outputs of the plurality of groups of flip flops being connected in an exclusive-or (XOR) arrangement, with a latch connected to the output of the DXOR. A metastable output of at least one of the flip flops causes a random signal to be output by the XOR for random number generation. The groups of flip flops can be divided into equally-sized groups, or unequally-sized groups with different configurations, such as the cross-connecting of NAND gates with or without buffers inserted between the data and clock signals, or inserting buffers between a data line of at least one NAND gate of each of the pairs of NAND gates being connected, or inserting a buffer between clock input of at least one NAND gate of each of the pairs of NAND gates being connected via a buffer. Capacitive loading and cross-connected buffers may also be used to induce varying delays.

Abstract: An apparatus, system and method for retaining the maximum speed of flip-flop metastability based random number generators includes a fixed delay unit having an input for receiving a common signal from a digital signal generator, and a variable delay unit having an input also for receiving the common signal from the digital signal generator. Each of the delay units is attached to the input of a respective logic gate. A frequency measurement of the occurrences of metastability, which is the speed of the random bit generation and delay tuning module 312 receives an output of one of the first NAND gates, checks the frequency of random number bit generation and updates the variable delay unit to according to predetermined criteria to tune the delay so as to maximize the speed of the random bit generation. An algorithm is used to determine whether the optimum delay is equal to, smaller or larger than the delay used to achieve the measured frequency.

Abstract: A data storage system comprises a storage element, and an encryption and decryption unit connected between a host and the storage element, and using a key that is generated in the data storage system.

Abstract: A random number generator includes a chain of pairs of D-type flip-flops 205, 215 . . . having D and L inputs, a chain of substantially identical cascaded upper buffers 210,220 . . . each having a predetermined delay d1 and respective output taps. There is a chain of substantially identical cascaded lower buffers 240,260 . . . each having a predetermined delay d2, and respective output taps, wherein d1?d2. A first one of the pair of D-type flip flops 205 has its D and L inputs connected to a respective output tap of one of the upper buffers 210 and a respective output tap of one of the lower buffers 240, and a second one of the pair of D-type flip flops has its D and L inputs connected to a respective output tap of one of the lower buffers 260 and a respective output of one of the upper buffers 215. The common clock input 201 is connected to the first inputs of both the cascaded upper buffers and the cascaded lower buffers 210, 220 . . . and 240, 260 . . . A metastability detector 275,280 285,290,295 . . .

Abstract: A random number generator includes a flip-flop, and a pair of independent free-running oscillators having a respective set of 4 switches controlled with a non-inverted and inverted output of the flip-flop. An output from each of the oscillators is fed back to their respective input via a delay device. The pair of oscillators each has a feedback loop switch, and a pair of cross gate switches, each of which respectively connects an input signal of one oscillator to an output of another oscillator of the pair of oscillators. When the feedback loop switches are open and the cross gate switches are closed, the pair of oscillators forming a flip-flop with positive feedback resolves to a logic state that in a metastable way, producing an unpredictable (random) logic signal.

Abstract: Further increases in the difficulty of importing to a secure domain digital content including watermarks which impose a degree of difficulty on illicit importing to the secure domain of the digital content is disclosed. Further increases in the degree of difficulty are necessary because the degree of difficulty associated with the watermarks is capable of being illicitly overcome by dividing the digital content being imported into segments that are so short that the watermarks cannot be reliably detected. In a recorder, recording is prevented by determining that adjacent activations of start and stop keys are such that the digital content has been so divided. In a playback unit, playback is prevented by determining that recorded sections are so short that the watermarks therein cannot be reliably detected.

Abstract: An apparatus and method for random number generation, including a plurality of cross-connected latches 210, 215, 220, 225, providing at least two latch outputs (latch1, latch0) is provided. A first XOR 261 receives the at least two latch outputs (latch0, latch1) as an input, and generates a mistake signal “E” when its inputs do not match from the at least two latch outputs (latch0, latch1) being at different logic states. The mistake signal is compared with a previously stored mistake signal by a second XOR 265 to determine whether to obtain a random bit from a pseudo random stream of bits.

Abstract: The present invention is a method and apparatus for testing random numbers generated by a random number generator in real time. As a series of random numbers are generated, a number of bits that have the value of a predetermined logic value at a specific, predefined range of intervals is determined and then applied to an exponential averaging operation (A). Thereafter, it is determined whether the generated random numbers are predictable by comparing the output of all said exponential operations to their predetermined acceptance range.

Abstract: Apparatus and methods for attacking a screening algorithm. Content to be downloaded is identified. The identified content is then partitioned into at least two sections, wherein each of the at least two sections has a duration which is less than a duration of a threshold duration value assigned by the screening algorithm, and the partitioned content is subjected to a screening algorithm. Once the content has been successfully downloaded, the integrity of the downloaded content may be restored by reassembling the sections.