Abstract: A signal translator circuit receives digital input signals of one voltage polarity and translates them to digital output signals of an opposite polarity. One embodiment of the translator converts conventional CMOS signal levels of +5 and 0 volts to modified CMOS signal levels of 0 and -5.2 volts. Another embodiment of the translator converts the 0 and -5.2 volt signals to the +5 and 0 volt signals. Both embodiments of the translator are made of transistors whose breakdown voltage only slightly exceeds +5 volts.

Abstract: An improved standard cell logic chip, of the type which contains one to fifteen thousand standard logic cells that are disposed in rows on a substrate, and has cell interconnect channels of different widths between the rows, also includes fast change logic cells which are sparsely distributed in the rows of standard logic cells. Each fast change cell selectively performs any one of several logic functions. These fast change logic cells are formed from the same stacked conductive and insulative layers as the standard logic cells; however, in the fast change cells, all conductive and insulative layers which are below at least the mid level in the stack of layers have respective patterns which are identical in every fast change cell. Only the remaining conductive and insulative layers in the fast change cells have respective patterns which differ from one fast change cell to another, and they select the logical functions which the fast change cells perform.

Abstract: A module for preventing instability in systems which test integrated circuit chips resides between the tester unit and the chip that is being tested. This module is characterized as including a plurality of phase-shifting circuits which couple respective output signals from output transistors on the chip onto signal lines to the tester unit. Each phase-shifting circuit includes an inductor which counteracts and cancels any capacitive phase shift that is produced by the input impedance of the corresponding signal line to the tester unit.

Abstract: A logic cell, for use in a semicustom chip, is comprised of a plurality of transistors that are integrated into a semiconductor substrate and are interconnected within the cell to perform a logic function. This cell has sidewalls which define the space in the chip which contains all the transistors and their interconnections within the cell; at least one of the sidewalls is shaped to include a step which gives the cell a narrow top and a wide bottom; and one or more of the cell's transistors lies below the step in the wide bottom of the cell. Many of these cells are arranged in spaced apart rows on the semicustom chip in which the narrow tops of the cell line up. Conductors which interconnect the cells are disposed in the space between the narrow tops of the cells and over the transistors in the wide bottoms of the cells. Using this architecture, the density with which a logic cell is integrated to a semicustom chip is improved more than 100%.

Abstract: A synchronizer is comprised of a voltage amplifier having an input terminal for receiving a voltage sample and an output terminal for generating an output voltage that is inversely proportional to the voltage of the input terminal. Also, a first feedback circuit couples the output terminal to a control transistor internal to the amplifier, and a second feedback circuit couples the output terminal to the input terminal. The first feedback circuit together with the control transistor has a fast response time, in comparison to the second feedback circuit; and it operates to quickly increase the output voltage when the voltage sample on the input terminal is below a predetermined level, and vice versa, without altering the voltage sample on the input terminal. And, the second feedback circuit operates to slowly modify the voltage sample on the input terminal in inverse proportion to the output terminal voltage.

Abstract: A two input nonsaturating bipolar logic gate consists of just two bipolar transistors plus a pair of resistors plus two voltage buses. One resistor has a resistance R.sub.C and it is connected from one of the voltage buses to the collector of both transistors. The second resistor has a resistance R.sub.E and it is connected from the other voltage bus to the emitter of both transistors. Those resistances R.sub.C and R.sub.E are selected such that R.sub.C /R.sub.E >1 and 0.1<(V.sub.CC -V.sub.BE)R.sub.C /R.sub.E <0.8 V.sub.BE where V.sub.BE is the base to emitter voltage at which each transistor turns on and V.sub.CC is the voltage between the two voltage buses.

Abstract: An integrated circuit having improved testability for defects includes a group of logic gates having respective input terminals and output terminals; a conductor that intercouples the output terminal of one logic gate in the group to respective input terminals on the remaining logic gates; a first via contact which, in the absence of a defect, couples the conductor through a first resistive device to a low voltage bus; a parasitic capacitor which couples the conductor to a high voltage bus; and a second via contact which, in the absence of a defect, couples the conductor through a second resistive device to the high voltage bus.

Abstract: A three-state logic circuit comprising a logic gate on a semiconductor chip which includes first and second conductors, respective resistors connected to the conductors, terminals for receiving input signals, and transistors for generating complementary output signals on the first and second conductors by passing respective currents through the resistors as a logical function of the input signals with the output signals having high and low voltage levels V.sub.H and V.sub.L ; a control circuit on the chip having a first terminal connected to the first conductor, a second terminal connected to the second conductor, and a control terminal for receiving a control signal; a switching circuit within the control circuit which responds to the control signal by passing identical control currents through the respective resistors and into the first and second terminals to thereby lower the voltage levels on both the first and second conductors by at least V.sub.H -V.sub.

Abstract: A circuit integrated into a substrate and having improved noise immunity comprises logic gates for receiving and switching current from a first bus to produce a logic signal; a resistor for receiving and passing a small bias current from a second bus indicating the state of the logic signal; a transistor for receiving and passing a large drive current from a third bus in response to bias current; and the first bus has a relatively large parasitic coupling serially through the logic gates, substrate, and resistors to the second bus; while the first bus has a relatively small parasitic coupling serially through the logic gates, substrate, and transistor to the third bus.

Abstract: A circuit having reduced susceptibility to noise includes a plurality of drivers coupled to a current bus; each driver receives a logic signal on a control terminal and operates to pass a large current when the logic signal is a one and pass a small current when the logic signal is a zero; the current bus has a parasitic inductance which generates a noise signal when the logic signals switch; noise on the current bus is parasitically coupled to the control terminal of each driver; and a plurality of noise reducing modules respectively couple to the control terminal of each driver and a common bus. Each module that receives a switching logic signal generates a control signal on the common bus that is similar in shape and opposite in polarity to the noise signal; and each module that does not receive a switching logic signal couples the control signal from the common bus to the control terminal to which it is connected.

Abstract: A magnetic bubble domain device nucleation source for producing magnetic bubble domains is disclosed, in which bubble domains along with possibly unwanted duplicate bubble domains are produced in response to a current pulse. A first bubble domain guide structure is provided which coupled and disposed directly adjacent the nucleator and defines a first bubble domain propagation path for guiding the movement of generated bubble domains in response to a cyclical change in orientation of a reorientating field within the plane of the magnetic layer. This first guide structure functions to receive bubble domains representative of information. More particularly, a second bubble domain guide structure is provided also disposed directly adjacent the nucleator and the first bubble domain guide structure.