Abstract: Some of the embodiments of the present disclosure provide a method for programming a flash memory having a plurality of memory blocks, wherein each memory block of the plurality of memory blocks is either a single-level cell (SLC) memory block or a multi-level cell (MLC) memory block, the method comprising assigning a weighting factor to each memory block of the plurality of memory blocks based on whether the memory block is an SLC memory block or an MLC memory block, tracking a number of write-erase cycles for each memory block, and selecting one or more memory blocks for writing data based at least in part on the weighting factor and the tracked number of write-erase cycles of each memory block of the plurality of memory blocks. Other embodiments are also described and claimed.

Abstract: Some of the embodiments of the present disclosure provide a method for programming a flash memory having a plurality of memory blocks, wherein each memory block of the plurality of memory blocks is either a single-level cell (SLC) memory block or a multi-level cell (MLC) memory block, the method comprising assigning a weighting factor to each memory block of the plurality of memory blocks based on whether the memory block is an SLC memory block or an MLC memory block, tracking a number of write-erase cycles for each memory block, and selecting one or more memory blocks for writing data based at least in part on the weighting factor and the tracked number of write-erase cycles of each memory block of the plurality of memory blocks. Other embodiments are also described and claimed.

Abstract: A solid state drive (SSD) includes an SSD control module configured to determine frequencies corresponding to how often data stored in respective logical addresses associated with the SSD is updated and form groups of the logical addresses according to the frequencies, and a memory control module configured to rewrite the data to physical addresses in blocks of an SSD storage region based on the groups.

Abstract: A storage module includes a first memory with blocks for storing first and second commands transmitted from a host to a storage module. The staging module determines, based on a first timer, whether the first command has been received from the host. If received, the first command is stored in a first block of the first memory. If not received, the first block is left empty. A timing module starts the first timer when the first block is left empty and starts a second timer for the first block when the first command is stored in the first block. A control module: executes the commands to transfer data between the host and a second memory based on storage of the commands; determines whether a second block is empty; if empty, waits for the second timer to expire; and if not empty, resets the first timer.

Abstract: An apparatus and other embodiments associated with solid-state drive command grouping are described. In one embodiment, an apparatus includes a hardware memory configured to store a plurality of commands that are to be executed on a solid-state drive. The apparatus also includes organization logic implemented with at least hardware and configured to arrange at least two commands of the plurality of commands into a command pack based, at least in part, on one or more attributes of the at least two commands.

Abstract: Some of the embodiments of the present disclosure provide a method for programming a flash memory having a plurality of memory blocks, wherein each memory block of the plurality of memory blocks is either a single-level cell (SLC) memory block or a multi-level cell (MLC) memory block, the method comprising assigning a weighting factor to each memory block of the plurality of memory blocks based on whether the memory block is an SLC memory block or an MLC memory block, tracking a number of write-erase cycles for each memory block, and selecting one or more memory blocks for writing data based at least in part on the weighting factor and the tracked number of write-erase cycles of each memory block of the plurality of memory blocks. Other embodiments are also described and claimed.

Abstract: A memory includes first memory configured to store first data indicating relationships between logical addresses and respective physical addresses, wherein the physical addresses are arranged in a plurality of different groups, respective statuses of each of the plurality of different groups, and an activity log indicating when any of the respective statuses has changed. A second memory is configured to store second data in memory locations corresponding to the physical addresses and, in response to a respective status of one of the plurality of groups changing, store a portion of the first data corresponding to the one of the plurality of groups. A recovery module is configured to update, in response to the activity log indicating that the respective status of the one of the plurality of groups has changed, the first data with the portion of the first data corresponding to the one of the plurality of groups.

Abstract: An integrated circuit including a first interface, a decoder, and a controller. The first interface is configured to (i) write encoded data in a portion of a flash memory, and (ii) read the encoded data back from the flash memory. The decoder is configured to (i) according to an error correction code, decode the encoded data read back from the flash memory, and (ii) based on the decoded data, determine a number of decoding errors corresponding to the decoded data. The controller is configured to, in response to the number of decoding errors being greater than or equal to a first threshold, cease accessing the portion of the flash memory. The first threshold is less than a number of errors correctable by the error correction code for the portion of the flash memory.

Abstract: Some of the embodiments of the present disclosure provide a method for programming a flash memory having a plurality of memory blocks, wherein each memory block of the plurality of memory blocks is either a single-level cell (SLC) memory block or a multi-level cell (MLC) memory block, the method comprising assigning a weighting factor to each memory block of the plurality of memory blocks based on whether the memory block is an SLC memory block or an MLC memory block, tracking a number of write-erase cycles for each memory block, and selecting one or more memory blocks for writing data based at least in part on the weighting factor and the tracked number of write-erase cycles of each memory block of the plurality of memory blocks. Other embodiments are also described and claimed.

Abstract: In first and second memories, respectively, data cannot and can be overwritten on prewritten locations without first erasing the prewritten locations. A selection module selects memory blocks of first memory, which are partially written with first data, in response to receiving a write command to write second data to the memory blocks. A control module, prior to erasing the first data from the memory blocks, writes the first data in a portion of second memory instead of writing the first data in first memory. A location description module generates a description table indicating whether data in memory locations in the portion of second memory are valid or invalid. A rate of adding data to the portion becomes equal to a rate at which data in memory locations in the portion becomes invalid so that the first data is written in the portion without first merging the first data.

Abstract: A method includes, in at least one aspect, receiving a command for a group of data units to be transmitted to a host in a first sequence; for each data unit of the group of data units, receiving an identifier of the data unit and a signal indicating that the data unit has been retrieved and processed for errors, wherein the identifiers and the signals are received in accordance with the group of data units being retrieved from one or more memory devices in a second sequence that is different from the first sequence; tracking the group of data units retrieved in the second sequence; determining, by processing circuitry, that the group of data units has been retrieved and processed for errors; and initiating transmission of the group of data units to the host in accordance with the first sequence.

Abstract: A storage drive includes a first integrated circuit, a second integrated circuit, an interface, an encoder, and a write module. The first integrated circuit includes a first array of memory cells. The second integrated circuit includes a second array of memory cells. The interface is connected to a host. The interface is configured to receive a first block of data transmitted from the host to the storage drive. The encoder is configured to encode the first block of data. The write module is configured to write (i) a first portion of the encoded first block of data to a first row of the first array of memory cells, and (ii) a second portion of the encoded first block of data to a first row of the second array of memory cells.

Abstract: A storage drive includes a first integrated circuit, a second integrated circuit, an interface, an encoder, and a write module. The first integrated circuit includes a first array of memory cells. The second integrated circuit includes a second array of memory cells. The interface is connected to a host. The interface is configured to receive a first block of data transmitted from the host to the storage drive. The encoder is configured to encode the first block of data. The write module is configured to write (i) a first portion of the encoded first block of data to a first row of the first array of memory cells, and (ii) a second portion of the encoded first block of data to a first row of the second array of memory cells.

Abstract: A method includes, in at least one aspect, receiving a command for a group of data units to be transmitted to a host in a first sequence; for each data unit of the group of data units, receiving an identifier of the data unit and a signal indicating that the data unit has been retrieved and processed for errors, wherein the identifiers and the signals are received in accordance with the group of data units being retrieved from one or more memory devices in a second sequence that is different from the first sequence; tracking the group of data units retrieved in the second sequence; determining, by processing circuitry, that the group of data units has been retrieved and processed for errors; and directing transmission of the group of data units to the host in accordance with the first sequence.

Abstract: A system includes a flash memory, an encoder, a first interface, a decoder and a controller. The encoder is configured to (i) receive data, and (ii) encode the data based on an error correction code. The first interface is configured to (i) write the encoded data to a memory cells in the flash memory, and (ii) read the encoded data back from the memory cells. The decoder is configured to (i) decode the encoded data read back from the memory cells, and (ii) based on the decoded data, determine a number of decoding errors for the plurality of memory cells. The controller is configured to, in response to the number of decoding errors being greater than or equal to a first threshold, cease accessing the memory cells. The first threshold is less than a maximum number of errors correctable by the error correction code for the memory cells.

Abstract: A selection module selects memory blocks of a flash memory in response to (i) the memory blocks being partially written with first data and (ii) receiving a write command to write second data to the memory blocks. A control module, prior to erasing the first data from the memory blocks, collects the first data and writes the collected data in a portion of a dynamic random access memory instead of writing the collected data in the flash memory. A location description module generates a description table indicating whether data in memory locations in the portion of the dynamic random access memory are valid or invalid. A rate of adding data to the portion becomes equal to a rate at which data in memory locations in the portion becomes invalid so that the collected data is written in the portion without first merging the collected data.

Abstract: A memory includes first memory configured to store first data indicating relationships between logical addresses and respective physical addresses, wherein the physical addresses are arranged in a plurality of different groups, respective statuses of each of the plurality of different groups, and an activity log indicating when any of the respective statuses has changed. A second memory is configured to store second data in memory locations corresponding to the physical addresses and, in response to a respective status of one of the plurality of groups changing, store a portion of the first data corresponding to the one of the plurality of groups. A recovery module is configured to update, in response to the activity log indicating that the respective status of the one of the plurality of groups has changed, the first data with the portion of the first data corresponding to the one of the plurality of groups.

Abstract: The present disclosure includes systems and techniques relating to solid state drive controllers. In some implementations, a device includes a buffer that holds a block of data corresponding to a command from a host. The command identifies the block of data and a logical sequence in which the identified block of data is to be transmitted. In response to the command, a data retriever included in the device retrieves the portions of the block of data from non-volatile memory units in a retrieval sequence that is different from the logical sequence. When the device receives multiple commands identifying multiple blocks of data, the device services the commands in parallel by retrieving portions of blocks of data identified by both commands.

Abstract: An apparatus and other embodiments associated with solid-state drive command grouping are described. In one embodiment, an apparatus includes a hardware memory configured to store a plurality of commands that are to be executed on a solid-state drive. The apparatus also includes organization logic implemented with at least hardware and configured to arrange at least two commands of the plurality of commands into a command pack based, at least in part, on one or more attributes of the at least two commands.

Abstract: A solid-state drive, a solid-state drive access unit allocation/data storage approach, and a solid-state drive access unit access/data retrieval approach are described that improve the efficiency with which data, that has been stored to the solid-state drive in association with a series of logical block addresses, can be retrieved from the solid-state drive. The described access unit allocation approach assures that data stored in the solid-state drive in association with a sequential series of logical block addresses is stored and maintained in solid-state drive access units, i.e., addressable units of solid-state drive memory that allow parallel read access to the data via parallel memory access I/O channels internal to the solid-state drive. In this manner, the time required to retrieve data associated with a sequential series of logical block addresses from corresponding access units within the solid-state drive is reduced.