Patents by Inventor Laura Conde-Canencia

Laura Conde-Canencia has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230187024
    Abstract: A method includes obtaining, for each type of nucleotide, a probability density function, the probability density functions being obtained from measurements of current drops produced during at least one passage of at least one sequence of reference nucleotides through a nanopore sequencer; obtaining measurements of current drops produced when the sequence of nucleotides to be decoded passes through the nanopore sequencer; calculating, for each measurement value considered and for each type of nucleotide of the B types of nucleotides, a piece of reliability information based on the probability density function obtained for the type of nucleotide considered; obtaining a decoded value identifying a type of nucleotide from the B types of DNA nucleotides, by applying a soft decoding algorithm with an error correction code to the current drop measurement and to the B pieces of reliability information obtained for the considered measurement value.
    Type: Application
    Filed: May 11, 2021
    Publication date: June 15, 2023
    Inventor: Laura CONDE-CANENCIA
  • Patent number: 10361723
    Abstract: A method is proposed for managing a parity-check node calculation unit of an error-correcting code decoder having a representation as a bipartite graph comprising at least one parity-check node, the parity-check node being configured to receive first and second input messages, and to produce an output message, the elements of the input and output messages of the parity-check node comprising a symbol and a measure of reliability associated with the symbol, the first and second input messages containing lists of elements ordered by their measure of reliability. The method comprises: initializing a plurality of nbub FIFO memories with elements calculated from combinations of elements of the first and second input messages, and iteratively determining the values of the output message.
    Type: Grant
    Filed: January 7, 2015
    Date of Patent: July 23, 2019
    Assignees: UNIVERSITE DE BRETAGNE SUD, CENTRE NATIONAL DE LA RECHERCE SCIENTIFIQUE—CNRS
    Inventors: Emmanuel Boutillon, Oussama Abassi, Laura Conde-Canencia
  • Publication number: 20160336967
    Abstract: A method is proposed for managing a parity-check node calculation unit of an error-correcting code decoder having a nrepresentation as a bipartite graph comprising at least one parity-check node, the parity-check node being configured to receive first and second input messages, and to produce an output message, the elements of the input and output messages of the parity-check N node comprising a symbol and a measure of reliability associated with the symbol, the first and second input messages containing lists of elements ordered by their measure of reliability. The method comprises: initializing a plurality of nbub FIFO memories with elements calculated from combinations of elements of the first and second input messages, and iteratively determining the values of the output message.
    Type: Application
    Filed: January 7, 2015
    Publication date: November 17, 2016
    Applicants: Universite de Bretagne SUD, Centre National de la Recherche Scientifique-CNRS
    Inventors: Emmanuel Boutillon, Oussama Abassi, Laura Conde-Canencia
  • Patent number: 9438305
    Abstract: The invention concerns a method for transmitting symbols of non binary error correcting code words via a transmission channel. The method comprises a first modulation associating each code word symbol of p bits with a sequence of at least 2p chips from 2p possible sequences, a second modulation to modulate the phase or amplitude of a carrier signal with the sequences associated with the code words, and a step of transmitting the modulated carrier signal via said transmission channel. According to the invention, the first modulation is a spread spectrum modulation of the cyclic code shift keying type using a basic pseudo-random sequence of at least 2p chips, the possible 2p sequences being obtained by a circular shift of the basic pseudo-random sequence and a cyclic prefix is inserted into each symbol to be transmitted.
    Type: Grant
    Filed: February 13, 2013
    Date of Patent: September 6, 2016
    Assignees: Universite de Bretagne SUD, Centre National de la Recherche Scientifique—CNRS
    Inventors: Emmanuel Boutillon, Laura Conde-Canencia, Oussama Abassi
  • Publication number: 20150003499
    Abstract: The invention concerns a method for transmitting symbols of non binary error correcting code words via a transmission channel. The method comprises a first modulation associating each code word symbol of p bits with a sequence of at leas 2p chips from 2p possible sequences a second modulation to modulate the phase or amplitude of a carrier signal with the sequences associated with the code words, and a step of transmitting the modulated carrier signal via said transmission channel. According to the invention the first modulation is a spread spectrum modulation of the cyclic code shift keying type using a basic pseudo-random sequence of at least 2p chips, the possible 2p sequences being obtained by a circular shift of the basic pseudo-random sequence and a cyclic prefix is inserted into each symbol to be transmitted.
    Type: Application
    Filed: February 13, 2013
    Publication date: January 1, 2015
    Inventors: Emmanuel Boutillon, Laura Conde-Canencia, Oussama Abassi
  • Patent number: 8645787
    Abstract: A method for controlling an elementary parity node of a decoder for decoding non-binary LDPC codes or a code decoder using at least one non-binary parity constraint, and to the corresponding elementary parity node. The elementary parity node receives first and second input lists (U1, U2) having nm elements sorted in ascending or descending order, nm being greater than 1, and gives an output list (Uout) of nm? elements sorted in said ascending or descending order, nm? being greater than 1, each element of the output list (Uout) being the result of a computing operation ? between an element of the first input list (U1) and an element of the second input list (U2). A limited number of candidates is selected for each element of the output list to be generated so as to reduce the number of operations to be carried out in the elementary parity node.
    Type: Grant
    Filed: May 5, 2010
    Date of Patent: February 4, 2014
    Assignees: Universite de Bretagne Sud, Centre National de la Recherche Scientifique-CNRS
    Inventors: Emmanuel Boutillon, Laura Conde-Canencia
  • Publication number: 20120240002
    Abstract: A method for controlling an elementary parity node of a decoder for decoding non-binary LDPC codes or a code decoder using at least one non-binary parity constraint, and to the corresponding elementary parity node. The elementary parity node receives first and second input lists (U1,U2) having nm elements sorted in ascending or descending order, nm being greater than 1, and gives an output list (Uout) of nm, elements sorted in said ascending or descending order, nm, being greater than 1, each element of the output list (Uout) being the result of a computing operation ? between an element of the first input list (U1) and an element of the second input list (U2). A limited number of candidates is selected for each element of the output list to be generated so as to reduce the number of operations to be carried out in the elementary parity node.
    Type: Application
    Filed: May 5, 2010
    Publication date: September 20, 2012
    Applicant: UNIVERSITE DE BRETAGNE SUD
    Inventors: Emmanuel Boutillon, Laura Conde-Canencia