Abstract: The present invention is an integrated system on a chip that combines wireless, graphics, and multimedia. The graphics and multimedia features may be programmed by the end user while restricting programmability of the wireless features.

Abstract: A printer pen carriage support for a printer is disclosed. The printer pen carriage support includes a cantilever that fits within a groove of a pen carriage and provides support for the pen carriage. Support structures, such as bushings or bearings, may be included to assist in pen carriage movement along the cantilever.

Abstract: A printer pen carriage support for a printer is disclosed. The printer pen carriage support includes a cantilever that fits within a groove of a pen carriage and provides support for the pen carriage. Support structures, such as bushings or bearings, may be included to assist in pen carriage movement along the cantilever.

Abstract: A thermal inkjet printer with firing nozzles perpendicular to the carriage motion has two motors: paper and carriage. These motors, alone or in concert, provide the power to the service station. The service station has separate wiping and pen cleaning functions. The wipers need to move across the pens in a direction that is perpendicular the carriage direction. Through the use of gears, the wipers can be made to clean the pens at the same time that the paper is being advanced and using the same motor source. For capping, the caps are moved into place as the pens come to rest. The motion of the pens themselves could easily push a lever that pushes the caps into place.

Abstract: The present invention is an integrated system on a chip that combines wireless, graphics, and multimedia. The graphics and multimedia features may be programmed by the end user while restricting programmability of the wireless features.

Abstract: A thermal inkjet printer with firing nozzles perpendicular to the carriage motion has two motors: paper and carriage. These motors, alone or in concert, provide the power to the service station. The service station has separate wiping and pen cleaning functions. The wipers need to move across the pens in a direction that is perpendicular the carriage direction. Through the use of gears, the wipers can be made to clean the pens at the same time that the paper is being advanced and using the same motor source. For capping, the caps are moved into place as the pens come to rest. The motion of the pens themselves could easily push a lever that pushes the caps into place.

Abstract: An off-hook state of a telephone associated with a computer is used in order to disable the power management unit of the computer to prevent premature power shutdown while the telephone is being used. A power-managed computer system includes a bus system, and a central processing unit coupled to the bus system. The central processing unit has a normal power mode and a power saving mode. A telephony interface coupled to the bus system has a port for coupling to a telephone system network. A power management unit is also coupled to the bus system and is responsive to bus system activity and to indicia of telephony interface activity. The power management unit causes the central processing unit to be in a power saving mode when both bus system activity and telephony interface activity are less than a predetermined level of activity.

Abstract: A universal asynchronous receiver/transmitter (UART) computer programming interface emulates three-wire interface control. A register select circuit is supplied with address signals from a host CPU and has a plurality of register outputs organized into first and second groups. One of these groups of outputs are those which are required for three-wire operation in communications devices; and these outputs are mapped to the appropriate communications devices or registers. The other group of outputs required for three-wire operation, but with no corresponding function in a communications device, are implemented by means of an UART emulator circuit producing a data output which is coupled to an internal data bus, along with the output of the registers for the communications devices.

Abstract: A single bit status register includes an input flip-flop, an asynchronous latch having an input coupled to an output of the input flip-flop, a comparator for comparing the outputs of the flip-flop and the latch, and an output stage which provides an error output when the comparator determines that the outputs of the flip-flop and the latch are not the same. In this fashion, it is known when a "read" of the status register is invalid due to the presence of the error output. Preferably, the register also includes a reset disabling mechanism which prevents the input flip-flop from being reset until a valid read has occurred. A n-bit status register includes n register sections, where each register section includes an input flip-flop, an asynchronous latch having an input coupled to an output of the input flip-flop, and a register section comparison mechanism for comparing the outputs of the flip-flop and the latch in that register section.

Abstract: An integrated circuit with power conservation includes a number of functional blocks, each of which includes digital circuitry and at least one output control line, and a power controller coupled to the control lines. The output control lines develop clock control signals based upon a functional block's knowledge of the direction of data flow. The power controller the reduces power by deactivating functional blocks that are not needed as indicated by the clock control signals. More specifically, a system with power conservation includes a number of functional blocks capable of processing data, each of the functional blocks including a modulated clock input and N+1 clock control lines which reflect the direction of data flow, where N is a number of neighbors of a particular functional block, and a clock controller having an input clock, the clock controller being coupled to the modulated clock inputs and the clock control lines of the functional blocks.

Abstract: A single bit status register includes an input flip-flop, an asynchronous latch having an input coupled to an output of the input flip-flop, a comparator for comparing the outputs of the flip-flop and the latch, and an output stage which provides an error output when the comparator determines that the outputs of the flip-flop and the latch are not the same. In this fashion, it is known when a "read" of the status register is invalid due to the presence of the error output. Preferably, the register also includes a reset disabling mechanism which prevents the input flip-flop from being reset until a valid read has occurred. A n-bit status register includes n register sections, where each register section includes an input flip-flop, an asynchronous latch having an input coupled to an output of the input flip-flop, and a register section comparison mechanism for comparing the outputs of the flip-flop and the latch in that register section.

Abstract: An asynchronous latch circuit characterized by a pair of D-type flip-flops and a D-type latch. Data is clocked into a first flip-flop by a system clock signal and the output of the first flip-flop is clocked into a second flip-flop by an asynchronous latch enable signal. A comparator compares the outputs of the first and second flip-flops and develops an error signal if the two are not the same. The error signal forces the output of the latch to a known condition rather than letting the output be indeterminate. In an asynchronous latch register an error signal from any one of the asynchronous latch circuits will force all of the latch circuits in the register to a known condition to eliminate race condition errors.

Abstract: An asynchronous latch circuit characterized by a pair of D-type flip-flops and a D-type latch. Data is clocked into a first flip-flop by a system clock signal and the output of the first flip-flop is clocked into a second flip-flop by an asynchronous latch enable signal. A comparator compares the outputs of the first and second flip-flops and develops an error signal if the two are not the same. The error signal forces the output of the latch to a known condition rather than letting the output be indeterminate. In an asynchronous latch register an error signal from any one of the asynchronous latch circuits will force all of the latch circuits in the register to a known condition to eliminate race condition errors.

Abstract: A logic level shifter characterized by a first inverting stage which shifts an input signal downwardly to a lower level, and a second inverting stage which shifts the lower level upwardly to an output signal level which is greater than the input signal level. Feedback from the output is used to virtually eliminate static current drain when the input logic level is 0. The method of the invention involves downwardly shifting an input range of voltages to a lower range of voltages, and then upwardly shifting the lower range of voltages to an output range of voltages which is greater than the input range of voltages. There is preferably a first inversion in the downward shift and a second inversion in the upward shift. A sensing step senses the output voltage to reduce the static current consumed by the process.

Abstract: An integrated circuit with power conservation includes a number of functional blocks, each of which includes a digital circuitry and at least one output control line, and a power controller coupled to the control lines. The output control lines develop clock control signals based upon a functional block's knowledge of the direction of data flow. The power controller the reduces power by deactivating functional blocks that are not needed as indicated by the clock control signals. More specifically, a system with power conservation includes a number of functional blocks capable of processing data, each of the functional blocks including a modulated clock input and N+1 clock control lines which reflect the direction of data flow, where N is a number of neighbors of a particular functional block, and a clock controller having an input clock, the clock controller being coupled to the modulated clock inputs and the clock control lines of the functional blocks.