Patents by Inventor Laura Marie Caulfield

Laura Marie Caulfield has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230342028
    Abstract: Zone hints for use with a zoned namespace (ZNS) storage device. Zone hints include one or more of a first hint indicating that a zone is part of a group of a plurality of zones, a second hint indicating that the zone is to be fast-filled, or a third hint indicating that the zone is associated with a background operation. The first hint is structured to instruct the ZNS storage device to allocate to the zone a first storage resources that are physically adjacent to second storage resources reserved for others of the plurality of zones. The second hint is structured to instruct the ZNS storage device to bypass a staging area when writing to the zone. The third hint is structured to instruct the ZNS storage device to deprioritizing at least one operation writing to the zone, or to bypass the staging area when writing to the zone.
    Type: Application
    Filed: September 28, 2021
    Publication date: October 26, 2023
    Inventors: Scott Chao-Chueh LEE, Vadim MAKHERVAKS, Madhav Himanshubhai PANDYA, Ioan OLTEAN, Laura Marie CAULFIELD, Lee Edward PREWITT
  • Patent number: 11093177
    Abstract: A system includes reception of a request from a first application to create a virtual open-channel solid state drive associated with a first bandwidth and first capacity, association, in response to the request, of block addresses of a virtual address space of the first application with block addresses of one or more blocks of a first one of a first plurality of channels of a first open-channel solid state drive and with block addresses of one or more blocks of a second one of the first plurality of channels, reception, from the first application, of a first I/O call associated with one or more block addresses of the virtual address space, determination of block addresses of one or more blocks of the first one of the first plurality of channels which are associated with the one or more block addresses of the virtual address space, and execution of the first I/O call on the determined block addresses of one or more blocks of the first one of the first plurality of channels.
    Type: Grant
    Filed: June 20, 2019
    Date of Patent: August 17, 2021
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Anirudh Badam, Badriddine Khessib, Laura Marie Caulfield, Mihail Gavril Tarta, Robin Andrew Alexander, Xiaozhong Xing, Zhe Tan, Jian Xu
  • Patent number: 10699798
    Abstract: The present invention extends to methods, systems, and computer program products for testing storage device power circuitry. A storage device controller includes an embedded test program. The storage device controller executes the test program in response to receiving a test command. In one aspect, the test program issues a plurality of different command patterns to test shared power circuitry of storage device components (e.g., shared by an array of NAND flash memory devices). The test program identifies a command pattern that causes a greatest total current draw. In another aspect, the test program issues a specified command pattern (possibly repeatedly) to shared power circuitry to determine if the shared power circuitry fails.
    Type: Grant
    Filed: December 5, 2016
    Date of Patent: June 30, 2020
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Laura Marie Caulfield, Mark Alan Santaniello, J. Michael Andrewartha, John J. Siegler
  • Publication number: 20190303047
    Abstract: A system includes reception of a request from a first application to create a virtual open-channel solid state drive associated with a first bandwidth and first capacity, association, in response to the request, of block addresses of a virtual address space of the first application with block addresses of one or more blocks of a first one of a first plurality of channels of a first open-channel solid state drive and with block addresses of one or more blocks of a second one of the first plurality of channels, reception, from the first application, of a first I/O call associated with one or more block addresses of the virtual address space, determination of block addresses of one or more blocks of the first one of the first plurality of channels which are associated with the one or more block addresses of the virtual address space, and execution of the first I/O call on the determined block addresses of one or more blocks of the first one of the first plurality of channels.
    Type: Application
    Filed: June 20, 2019
    Publication date: October 3, 2019
    Inventors: Anirudh BADAM, Badriddine KHESSIB, Laura Marie CAULFIELD, Mihail Gavril TARTA, Robin Andrew ALEXANDER, Xiaozhong XING, Zhe TAN, Jian XU
  • Patent number: 10423361
    Abstract: A system includes reception of a request from a first application to create a virtual open-channel solid state drive associated with a first bandwidth and first capacity, association, in response to the request, of block addresses of a virtual address space of the first application with block addresses of one or more blocks of a first one of a first plurality of channels of a first open-channel solid state drive and with block addresses of one or more blocks of a second one of a second plurality of channels of a second open-channel solid state drive, reception, from the first application, of a first I/O call associated with one or more block addresses of the virtual address space, determination of block addresses of one or more blocks of the first one of the first plurality of channels which are associated with the one or more block addresses of the virtual address space, and execution of the first I/O call on the determined block addresses of one or more blocks of the first one of the first plurality of chan
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: September 24, 2019
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Anirudh Badam, Badriddine Khessib, Laura Marie Caulfield, Mihail Gavril Tarta, Robin Andrew Alexander, Xiaozhong Xing, Zhe Tan, Jian Xu
  • Publication number: 20190196748
    Abstract: A system includes reception of a request from a first application to create a virtual open-channel solid state drive associated with a first bandwidth and first capacity, association, in response to the request, of block addresses of a virtual address space of the first application with block addresses of one or more blocks of a first one of a first plurality of channels of a first open-channel solid state drive and with block addresses of one or more blocks of a second one of a second plurality of channels of a second open-channel solid state drive, reception, from the first application, of a first I/O call associated with one or more block addresses of the virtual address space, determination of block addresses of one or more blocks of the first one of the first plurality of channels which are associated with the one or more block addresses of the virtual address space, and execution of the first I/O call on the determined block addresses of one or more blocks of the first one of the first plurality of chan
    Type: Application
    Filed: December 21, 2017
    Publication date: June 27, 2019
    Inventors: Anirudh BADAM, Badriddine KHESSIB, Laura Marie CAULFIELD, Mihail Gavril TARTA, Robin Andrew ALEXANDER, Xiaozhong XING, Zhe TAN, Jian XU
  • Patent number: 10120573
    Abstract: An improved interface for managing disparate read, write, and erase sizes and operations in data storage devices is provided. By improving an interface between a storage system driver layer and associated storage devices, performance of data storage is improved, including improving data storage speed and storage media endurance. Storage media management operations are made more efficient and consistent by providing improved types and sequences of commands sent from the driver layer to the device control layer such that data write operations are performed in a sequential manner as write commands are directed to portions of data as opposed to buffering individual portions of data followed by a large wholescale write/erase process for the buffered data.
    Type: Grant
    Filed: April 28, 2016
    Date of Patent: November 6, 2018
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC.
    Inventors: Robin Alexander, Lee Edward Prewitt, William R. Tipton, Laura Marie Caulfield
  • Patent number: 10078455
    Abstract: Aspects extend to methods, systems, and computer program products for predicting solid state drive reliability. Aspects of the invention can be used to predict and/or to configure a data center to minimize one or more of: SSD capacity degradation (how much storage an SSD has left), SSD performance degradation (reduced read/write latency/throughput), and SSD failure. Models and data center considerations can be based on device level SSD related operations, such as, for example, read, write, erase. Operations decisions can be made for a data center based on SSD specific features, such as, for example, remaining capacity, write amplification factor, etc. Dependence and/or causality of various different data center factors can be leveraged. The impact of the various data center factors on different SSD failure modes and capacity/performance degradation can be quantified to drive SSD design, SSD provisioning, and SSD operations.
    Type: Grant
    Filed: January 20, 2016
    Date of Patent: September 18, 2018
    Inventors: Iyswarya Narayanan, Di Wang, Myeongjae Jeon, Bikash Sharma, Laura Marie Caulfield, Sriram Govindan, Benjamin Franklin Cutler, Christopher W. Hoder, Jaya Naga Satish Bobba, Jie Liu, Badriddine Khessib
  • Publication number: 20180232151
    Abstract: Operations of a variety of components of a storage system stack are redefined to make the system more efficient when the underlying media has a “multi-log” type interface such as the case with NAND flash SSD memory or shingled magnetic recording media. The responsibilities of components of the storage system stack are modified such that each responsibility is performed at the most efficient component (level of abstraction) of the storage stack.
    Type: Application
    Filed: April 16, 2018
    Publication date: August 16, 2018
    Applicant: Microsoft Technology Licensing, LLC.
    Inventors: Anirudh Badam, Bikash Sharma, Laura Marie Caulfield, Badriddine Khessib, Suman Kumar Nath, Jian Huang
  • Patent number: 9952769
    Abstract: Operations of a variety of components of a storage system stack are redefined to make the system more efficient when the underlying media has a “multi-log” type interface such as the case with NAND flash SSD memory or shingled magnetic recording media. The responsibilities of components of the storage system stack are modified such that each responsibility is performed at the most efficient component (level of abstraction) of the storage stack.
    Type: Grant
    Filed: April 28, 2016
    Date of Patent: April 24, 2018
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC.
    Inventors: Anirudh Badam, Bikash Sharma, Laura Marie Caulfield, Badriddine Khessib, Suman Kumar Nath, Jian Huang
  • Patent number: 9916273
    Abstract: Obtaining data about a peripheral device deployed in a computing environment. A method includes transmitting a primary data stream across a shared communication channel between the peripheral device and a host hosting the peripheral device. The method further includes transmitting on the shared communication channel, a secondary state information stream of consecutively occurring messages with peripheral device state information.
    Type: Grant
    Filed: July 10, 2015
    Date of Patent: March 13, 2018
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Christopher James Robinson, Laura Marie Caulfield, Brian Charles Coyne, Mukesh Cooblal, Mark Alan Santaniello
  • Publication number: 20170206026
    Abstract: Aspects extend to methods, systems, and computer program products for predicting solid state drive reliability. Aspects of the invention can be used to predict and/or to configure a data center to minimize one or more of: SSD capacity degradation (how much storage an SSD has left), SSD performance degradation (reduced read/write latency/throughput), and SSD failure. Models and data center considerations can be based on device level SSD related operations, such as, for example, read, write, erase. Operations decisions can be made for a data center based on SSD specific features, such as, for example, remaining capacity, write amplification factor, etc. Dependence and/or causality of various different data center factors can be leveraged. The impact of the various data center factors on different SSD failure modes and capacity/performance degradation can be quantified to drive SSD design, SSD provisioning, and SSD operations.
    Type: Application
    Filed: January 20, 2016
    Publication date: July 20, 2017
    Inventors: Iyswarya Narayanan, Di Wang, Myeongjae Jeon, Bikash Sharma, Laura Marie Caulfield, Sriram Govindan, Benjamin Franklin Cutler, Christopher W. Hoder, Jaya Naga Satish Bobba, Jie Liu, Badriddine Khessib
  • Publication number: 20170098479
    Abstract: The present invention extends to methods, systems, and computer program products for testing storage device power circuitry. A storage device controller includes an embedded test program. The storage device controller executes the test program in response to receiving a test command In one aspect, the test program issues a plurality of different command patterns to test shared power circuitry of storage device components (e.g., shared by an array of NAND flash memory devices). The test program identifies a command pattern that causes a greatest total current draw. In another aspect, the test program issues a specified command pattern (possibly repeatedly) to shared power circuitry to determine if the shared power circuitry fails.
    Type: Application
    Filed: December 5, 2016
    Publication date: April 6, 2017
    Inventors: Laura Marie Caulfield, Mark Alan Santaniello, J. Michael Andrewartha, John J. Siegler
  • Publication number: 20170075594
    Abstract: Operations of a variety of components of a storage system stack are redefined to make the system more efficient when the underlying media has a “multi-log” type interface such as the case with NAND flash SSD memory or shingled magnetic recording media. The responsibilities of components of the storage system stack are modified such that each responsibility is performed at the most efficient component (level of abstraction) of the storage stack.
    Type: Application
    Filed: April 28, 2016
    Publication date: March 16, 2017
    Applicant: Microsoft Technology Licensing, LLC.
    Inventors: Anirudh Badam, Bikash Sharma, Laura Marie Caulfield, Badriddine Khessib, Suman Kumar Nath, Jian Huang
  • Publication number: 20170075583
    Abstract: An improved interface for managing disparate read, write, and erase sizes and operations in data storage devices is provided. By improving an interface between a storage system driver layer and associated storage devices, performance of data storage is improved, including improving data storage speed and storage media endurance. Storage media management operations are made more efficient and consistent by providing improved types and sequences of commands sent from the driver layer to the device control layer such that data write operations are performed in a sequential manner as write commands are directed to portions of data as opposed to buffering individual portions of data followed by a large wholescale write/erase process for the buffered data.
    Type: Application
    Filed: April 28, 2016
    Publication date: March 16, 2017
    Applicant: Microsoft Technology Licensing, LLC.
    Inventors: Robin Alexander, Lee Edward Prewitt, William R. Tipton, Laura Marie Caulfield
  • Patent number: 9558848
    Abstract: The present invention extends to methods, systems, and computer program products for testing storage device power circuitry. A storage device controller includes an embedded test program. The storage device controller executes the test program in response to receiving a test command. In one aspect, the test program issues a plurality of different command patterns to test shared power circuitry of storage device components (e.g., shared by an array of NAND flash memory devices). The test program identifies a command pattern that causes a greatest total current draw. In another aspect, the test program issues a specified command pattern (possibly repeatedly) to shared power circuitry to determine if the shared power circuitry fails.
    Type: Grant
    Filed: November 4, 2014
    Date of Patent: January 31, 2017
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Laura Marie Caulfield, Mark Alan Santaniello, J. Michael Andrewartha, John J. Siegler
  • Publication number: 20170010995
    Abstract: Obtaining data about a peripheral device deployed in a computing environment. A method includes transmitting a primary data stream across a shared communication channel between the peripheral device and a host hosting the peripheral device. The method further includes transmitting on the shared communication channel, a secondary state information stream of consecutively occurring messages with peripheral device state information.
    Type: Application
    Filed: July 10, 2015
    Publication date: January 12, 2017
    Inventors: Christopher James Robinson, Laura Marie Caulfield, Brian Charles Coyne, Mukesh Cooblal, Mark Alan Santaniello
  • Publication number: 20160125958
    Abstract: The present invention extends to methods, systems, and computer program products for testing storage device power circuitry. A storage device controller includes an embedded test program. The storage device controller executes the test program in response to receiving a test command. In one aspect, the test program issues a plurality of different command patterns to test shared power circuitry of storage device components (e.g., shared by an array of NAND flash memory devices). The test program identifies a command pattern that causes a greatest total current draw. In another aspect, the test program issues a specified command pattern (possibly repeatedly) to shared power circuitry to determine if the shared power circuitry fails.
    Type: Application
    Filed: November 4, 2014
    Publication date: May 5, 2016
    Inventors: Laura Marie Caulfield, Mark Alan Santaniello, J. Michael Andrewartha, John J. Siegler